Debanjan Bhowmik

Orcid: 0000-0003-1136-8778

According to our database1, Debanjan Bhowmik authored at least 16 papers between 2018 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2025
Improved Performance of Multi-Angle Quantum Approximate Optimization Algorithm (ma-QAOA) Compared to QAOA On Simulation and Experimental Hardware Platforms.
Proceedings of the 17th International Conference on COMmunication Systems and NETworks, 2025

Variational Quantum Factorization (VQF) using Different Variations of Quantum Approximate Optimization Algorithm (QAOA).
Proceedings of the 17th International Conference on COMmunication Systems and NETworks, 2025

2024
Spin-coated ALPO-RRAM with Switching Speed < 50 ns and Nonlinearity 0.5.
Proceedings of the Device Research Conference, 2024

2023
Impact of edge defects on the synaptic characteristic of a ferromagnetic domain-wall device and on on-chip learning.
Neuromorph. Comput. Eng., September, 2023

2022
Fast-QTrain: an algorithm for fast training of variational classifiers.
Quantum Inf. Process., 2022

On-chip learning of a domain-wall-synapse-crossbar-array-based convolutional neural network.
Neuromorph. Comput. Eng., 2022

2021
Kuramoto-model-based data classification using the synchronization dynamics of uniform-mode spin Hall nano-oscillators.
Neuromorph. Comput. Eng., 2021

A Crossbar Array of Analog-Digital-Hybrid Volatile Memory Synapse Cells for Energy-Efficient On-Chip Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Quantum Activation Function for Neural Networks: Proposal and Implementation.
Proceedings of the International Joint Conference on Neural Networks, 2021

2020
Supervised learning with a quantum classifier using multi-level systems.
Quantum Inf. Process., 2020

Supervised Learning Using a Dressed Quantum Network with "Super Compressed Encoding": Algorithm and Quantum-Hardware-Based Implementation.
CoRR, 2020

Design of a Conventional-Transistor-Based Analog Integrated Circuit for On-Chip Learning in a Spiking Neural Network.
Proceedings of the International Conference on Neuromorphic Systems, 2020

Reduction of the Weight-Decay Rate of Volatile Memory Synapses in an Analog Hardware Neural Network for Accurate and Scalable On-Chip Learning.
Proceedings of the International Conference on Neuromorphic Systems, 2020

2019
Comparing domain wall synapse with other Non Volatile Memory devices for on-chip learning in Analog Hardware Neural Network.
CoRR, 2019

On-chip Learning In A Conventional Silicon MOSFET Based Analog Hardware Neural Network.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018
On-chip learning for domain wall synapse based Fully Connected Neural Network.
CoRR, 2018


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