Nilabjo Dey

According to our database1, Nilabjo Dey authored at least 2 papers between 2019 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2020
Reduction of the Weight-Decay Rate of Volatile Memory Synapses in an Analog Hardware Neural Network for Accurate and Scalable On-Chip Learning.
Proceedings of the International Conference on Neuromorphic Systems, 2020

2019
On-chip Learning In A Conventional Silicon MOSFET Based Analog Hardware Neural Network.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019


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