Utkarsh Saxena

Orcid: 0009-0007-0042-2413

According to our database1, Utkarsh Saxena authored at least 12 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Hardware/Software Co-Design With ADC-Less In-Memory Computing Hardware for Spiking Neural Networks.
IEEE Trans. Emerg. Top. Comput., 2024

HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloads.
CoRR, 2024

2023
Partial-Sum Quantization for Near ADC-Less Compute-In-Memory Accelerators.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

McQueen: Mixed Precision Quantization of Early Exit Networks.
Proceedings of the 34th British Machine Vision Conference 2023, 2023

2022
Compute-in-Memory Technologies and Architectures for Deep Learning Workloads.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Towards ADC-Less Compute-In-Memory Accelerators for Energy Efficient Deep Learning.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Embracing Stochasticity to Enable Neuromorphic Computing at the Edge.
IEEE Des. Test, 2021

2020
Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Augmenting smart home network security using blockchain technology.
Int. J. Electron. Secur. Digit. Forensics, 2020

Prediction of Syncope based on Physiological Data Analysis using Decision Tree Algorithm.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

2019
On-chip Learning In A Conventional Silicon MOSFET Based Analog Hardware Neural Network.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018
On-chip learning for domain wall synapse based Fully Connected Neural Network.
CoRR, 2018


  Loading...