Ankesh Jain
Orcid: 0000-0003-4109-6312
According to our database1,
Ankesh Jain
authored at least 23 papers
between 2011 and 2024.
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Bibliography
2024
Hybrid Piezoelectric-Triboelectric Biomechanical Harvesting System for Wearable Applications.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
2023
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
2021
Electrical Energy Injection using Hybrid SECE for High Performance Nonlinear Mechanical Energy Harvesting.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
High speed Continuous-time Delta Sigma Modulators for Wide-band Applications: A review paper.
Proceedings of the 18th International SoC Design Conference, 2021
2020
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance.
IEEE J. Solid State Circuits, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Reduction of the Weight-Decay Rate of Volatile Memory Synapses in an Analog Hardware Neural Network for Accurate and Scalable On-Chip Learning.
Proceedings of the International Conference on Neuromorphic Systems, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
An Integrated Readout for Current Sensing based on a Σ∆ Modulator with Switched Capacitor Feedback.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 0.4-V G<sub>m</sub>-C Proportional-Integrator-Based Continuous-Time ΔΣ Modulator With 50-kHz BW and 74.4-dB SNDR.
IEEE J. Solid State Circuits, 2018
A High-Resolution Delta-Sigma D/A Converter Architecture with High Tolerance to DAC Mismatch.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Gain Mismatch Insensitive Time-Interleaved DAC for CT Delta Sigma Modulator by application of a Three-State DAC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Interferer Induced Jitter Reduction in Bandpass CT ΣΔ Modulators for Receiver Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the 10th International Workshop on Network on Chip Architectures, 2017
2016
A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
2013
Improved characterization of high speed continuous-time ΔΣ modulators using a duobinary test interface.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Analysis and Design of a High Speed Continuous-time ΔΣ Modulator Using the Assisted Opamp Technique.
IEEE J. Solid State Circuits, 2012
2011
A 4mW 1 GS/s continuous-time ΔΣ modulator with 15.6MHz bandwidth and 67 dB dynamic range.
Proceedings of the 37th European Solid-State Circuits Conference, 2011