Deokjin Joo
According to our database1,
Deokjin Joo
authored at least 11 papers
between 2011 and 2017.
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Bibliography
2017
Kapre: On-GPU Audio Preprocessing Layers for a Quick Implementation of Deep Neural Network Models with Keras.
CoRR, 2017
2016
Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes.
Integr., 2016
Clock buffer polarity assignment utilizing useful clock skews for power noise reduction.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2014
A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
2013
An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
2011
Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the International SoC Design Conference, 2011
WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing.
Proceedings of the 48th Design Automation Conference, 2011