Hochang Jang

According to our database1, Hochang Jang authored at least 2 papers between 2009 and 2011.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2011
Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2009
Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization.
Proceedings of the 46th Design Automation Conference, 2009


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