Diego Peña-Colaiocco

According to our database, Diego Peña-Colaiocco authored at least 6 papers between 2020 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains.

Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, Visvesh S. Sathe

IEEE J. Solid State Circuits, 2023

2022

An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS.

Diego Peña-Colaiocco, Chi-Hsiang Huang, Kun-Da Chu, Jacques Christophe Rudell, Visvesh S. Sathe

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains.

Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, Visvesh S. Sathe

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A Reconfigurable Digital Beamforming V-Band Phased-Array Receiver.

Deniz Dosluoglu, Kun-Da Chu, Diego Peña-Colaiocco, Ivan Zhao, Visvesh Sathe, Jacques C. Rudell

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2020

UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS.

Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang, Diego Peña-Colaiocco, Visvesh S. Sathe

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS.

Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang, Diego Peña-Colaiocco, Visvesh S. Sathe

Proceedings of the IEEE Symposium on VLSI Circuits, 2020