Chi-Hsiang Huang
Orcid: 0000-0003-4147-4643Affiliations:
- University of Washington, Processing Systems Laboratory, Seattle, WA, USA
- National Cheng Kung University, Department of Electrical Engineering, Tainan, Taiwan (former)
According to our database1,
Chi-Hsiang Huang
authored at least 9 papers
between 2018 and 2023.
Collaborative distances:
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Bibliography
2023
Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains.
IEEE J. Solid State Circuits, 2023
2022
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control.
IEEE J. Solid State Circuits, 2022
An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
Bidirectional Single-Inductor Dual-Supply Converter With Automatic State-Transition for IoT Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2018
IEEE J. Solid State Circuits, 2018