Dieu Van Dinh

According to our database1, Dieu Van Dinh authored at least 3 papers between 2000 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2021
A Design Approach to Reduce Test Time on SOC Memories.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

2005
Meeting the Test Challenges of the 1 Gbps Parallel RapidIO Interface with New Automatic Test Equipment Capabilities.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

2000
An approach to testing 200 ps echo clock to output timing on the double data rate synchronous memory.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000


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