Prokash Ghosh

Orcid: 0009-0008-8657-1555

According to our database1, Prokash Ghosh authored at least 17 papers between 2012 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Exception Coverage on Automotive Processors.
IEEE Embed. Syst. Lett., February, 2026

An Efficient Memory Cell Flipping Technique Under Covert Channel Attacks.
Proceedings of the 27th International Symposium on Quality Electronic Design, 2026

2025
FLASH: Deadline-Aware Flexible LLC Arbitration and Scheduling for Hardware Accelerators.
ACM Trans. Embed. Comput. Syst., November, 2025

On Enhancing the Security Against Memory Disclosure Attacks.
Proceedings of the 38th IEEE International System-on-Chip Conference, 2025

2024
Application-Aware Memory Management for IPsec on Heterogeneous SoCs.
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design - 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

APPAMM: Memory Management for IPsec Application on Heterogeneous SoCs.
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

2023
Self-Checking Performance Verification Methodology for Complex SoCs.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

On-Chip SRAM Disclosure Attack Prevention Technique for SoC.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

2021
A Framework for Evaluation of Debug Path Performance in SoC.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

A Design Approach to Reduce Test Time on SOC Memories.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

2020
A Novel Approach of Data Content Zeroization Under Memory Attacks.
J. Electron. Test., 2020

2019
An Efficient Memory Zeroization Technique Under Side-Channel Attacks.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Case Study: SoC Performance Verification and Static Verification of RTL Parameters.
Proceedings of the 20th International Workshop on Microprocessor/SoC Test, 2019

2017
A Configurable and Area Efficient Technique for Implementing Isolation Cells in Low Power SoC.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2015
Case study: Re-visiting SoC verification challenges and best practices.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2013
Enhancement of Production Pattern Development Methodology and Best Practices.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

2012
Dynamic Sharing of On-Chip Scratchpad Memory on Embedded Platforms.
Proceedings of the International Symposium on Electronic System Design, 2012


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