Dimitrios Mangiras

Orcid: 0000-0002-3602-5862

According to our database1, Dimitrios Mangiras authored at least 8 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
Task-Based Parallel Programming for Gate Sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

2021
Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment.
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021

2020
Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop Clustering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

2019
Multi-Armed Bandits for Autonomous Timing-driven Design Optimization.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

Dynamic Adjustment of Test-Sequence Duration for Increasing the Functional Coverage.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019


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