Giorgos Dimitrakopoulos
Orcid: 0000-0003-3688-7865
According to our database1,
Giorgos Dimitrakopoulos
authored at least 86 papers
between 2002 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity.
IEEE Comput. Archit. Lett., 2024
2023
IEEE Trans. Very Large Scale Integr. Syst., November, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
IEEE Trans. Very Large Scale Integr. Syst., March, 2023
Microprocess. Microsystems, 2023
IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications.
CoRR, 2023
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023
Multi-Armed Bandits for Autonomous Test Application in RISC-V Processor Verification.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022
IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
LeapConv: An Energy-Efficient Streaming Convolution Engine with Reconfigurable Stride.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
FusedGCN: A Systolic Three-Matrix Multiplication Architecture for Graph Convolutional Networks.
Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022
2021
Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching.
Integr., 2021
Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment.
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop Clustering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020
Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
SmartFork: Partitioned Multicast Allocation and Switching in Network-on-Chip Routers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Memristive Oscillatory Circuits for Resolution of NP-Complete Logic Puzzles: Sudoku Case.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD).
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019
Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension.
Microprocess. Microsystems, 2018
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Active Thermoelectric Cooling Solutions for Airspace Applications: the THERMICOOL Project.
IEEE Access, 2017
Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling.
Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2017
Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE Trans. Computers, 2016
An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures.
ACM Trans. Archit. Code Optim., 2016
Powermax: an automated methodology for generating peak-power traffic in networks-on-chip.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
The fast evolving landscape of on-chip communication - Selected future challenges and research avenues.
Des. Autom. Embed. Syst., 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
IEEE Trans. Computers, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Proceedings of the 2012 Interconnection Network Architecture, 2012
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Proceedings of the Fifth International Workshop on Interconnection Network Architecture, 2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
2009
A management scheme for improving transportation efficiency and contributing to the enhancement of the social fabric.
Telematics Informatics, 2009
2008
Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units.
IEEE Trans. Very Large Scale Integr. Syst., 2008
Proceedings of the 26th International Conference on Computer Design, 2008
Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation.
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
2005
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the 12th IEEE International Conference on Electronics, 2005
2004
A novel architecture and a systematic graph-based optimization methodology for modulo multiplication.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
Proceedings of the Integrated Circuit and System Design, 2004
2003
A systematic methodology for designing area-time efficient parallel-prefix modulo 2<sup>n</sup> - 1 adders.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003
2002
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002