Chrysostomos Nicopoulos

According to our database1, Chrysostomos Nicopoulos authored at least 77 papers between 2005 and 2020.

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Bibliography

2020
The Mesochronous Dual-Clock FIFO Buffer.
IEEE Trans. VLSI Syst., 2020

2019
Automatic Generation of Peak-Power Traffic for Networks-on-Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Multi-Armed Bandits for Autonomous Timing-driven Design Optimization.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

Dynamic Adjustment of Test-Sequence Duration for Increasing the Functional Coverage.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019

Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension.
Microprocess. Microsystems, 2018

Exploring System Availability During Software-Based Self-Testing of Multi-core CPUs.
J. Electronic Testing, 2018

Fast Estimations of Failure Probability Over Long Time Spans.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Low-power dual-edge-triggered synchronous latency-insensitive systems.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Hardware-Based Online Self-Diagnosis for Faulty Device Identification in Large-Scale IoT Systems.
Proceedings of the 2018 IEEE/ACM Third International Conference on Internet-of-Things Design and Implementation, 2018

2017
HoPE: Hot-Cacheline Prediction for Dynamic Early Decompression in Compressed LLCs.
ACM Trans. Design Autom. Electr. Syst., 2017

Networks-on-Chip With Double-Data-Rate Links.
IEEE Trans. on Circuits and Systems, 2017

A Dual-Clock Multiple-Queue Shared Buffer.
IEEE Trans. Computers, 2017

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers.
J. Parallel Distributed Comput., 2017

A Design Space Exploration Framework for ANN-Based Fault Detection in Hardware Systems.
J. Electrical and Computer Engineering, 2017

Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling.
Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2017


2016
PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

DaemonGuard: Enabling O/S-Orchestrated Fine-Grained Software-Based Selective-Testing in Multi-/Many-Core Microprocessors.
IEEE Trans. Computers, 2016

ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing.
IEEE Trans. Computers, 2016

An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures.
TACO, 2016

Toward Multi-Layer Holistic Evaluation of System Designs.
Computer Architecture Letters, 2016

Powermax: an automated methodology for generating peak-power traffic in networks-on-chip.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

RapidLink: A network-on-chip architecture with double-data-rate links.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

CrossOver: Clock domain crossing under virtual-channel flow control.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip.
IEEE Trans. VLSI Syst., 2015

Size-Aware Cache Management for Compressed Cache Architectures.
IEEE Trans. Computers, 2015

Subtleties of Run-Time VirtualAddress Stacks.
Computer Architecture Letters, 2015

HARPA: Solutions for dependable performance under physically induced performance variability.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Toward efficient check-pointing and rollback under on-demand SBST in chip multi-processors.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Timing-resilient Network-on-Chip architectures.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Designing Hybrid DRAM/PCM Main Memory Systems Utilizing Dual-Phase Compression.
ACM Trans. Design Autom. Electr. Syst., 2014

Centaur: a hybrid network-on-chip architecture utilizing micro-network fusion.
Design Autom. for Emb. Sys., 2014

ElastiNoC: A self-testable distributed VC-based Network-on-Chip architecture.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Exploration of system availability during software-based self-testing in many-core systems under test latency constraints.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

ElastiStore: An elastic buffer architecture for Network-on-Chip routers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures.
IEEE Trans. VLSI Syst., 2013

TornadoNoC: A lightweight and scalable on-chip network architecture for the many-core era.
TACO, 2013

Sharded Router: A novel on-chip router architecture employing bandwidth sharding and stealing.
Parallel Comput., 2013

Dynamic fault-tolerant routing algorithm for networks-on-chip based on localised detouring paths.
IET Computers & Digital Techniques, 2013

Do we need wide flits in Networks-on-Chip?
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Hardware-Assisted Intrusion Detection by Preserving Reference Information Integrity.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2013

ECM: Effective Capacity Maximizer for high-performance compressed caching.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

DaemonGuard: O/S-assisted selective software-based Self-Testing for multi-core systems.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Switch folding: network-on-chip routers with time-multiplexed output ports.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
A Dynamically Adjusting Gracefully Degrading Link-Level Fault-Tolerant Mechanism for NoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Optimizing Data-Center TCO with Scale-Out Processors.
IEEE Micro, 2012

NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

A Compression-Based Hybrid MLC/SLC Management Technique for Phase-Change Memory Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Virtualizing Virtual Channels for Increased Network-on-Chip Robustness and Upgradeability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Thermal characterization of cloud workloads on a power-efficient server-on-chip.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

A dual-phase compression mechanism for hybrid DRAM/PCM main memory architectures.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

A programmable processing array architecture supporting dynamic task scheduling and module-level prefetching.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

2011
Variation-Aware Task and Communication Mapping for MPSoC Architecture.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Hardware-Based Job Queue Management for Manycore Architectures and OpenMP Environments.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Large-Scale Semantic Concept Detection on Manycore Platforms for Multimedia Mining.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

A High-Performance and Energy-Efficient Virtually Tagged Stack Cache Architecture for Multi-core Environments.
Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011

2010
Network-on-Chip Architectures - A Holistic Design Exploration
Lecture Notes in Electrical Engineering 45, Springer, ISBN: 978-90-481-3030-6, 2010

On the Effects of Process Variation in Network-on-Chip Architectures.
IEEE Trans. Dependable Sec. Comput., 2010

A fine-grained link-level fault-tolerant mechanism for networks-on-chip.
Proceedings of the 28th International Conference on Computer Design, 2010

2009
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs.
TRETS, 2009

2008
Performance and power optimization through data compression in Network-on-Chip architectures.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

Analysis and solutions to issue queue process variation.
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

Design space exploration for field programmable compressor trees.
Proceedings of the 2008 International Conference on Compilers, 2008

2007
A novel dimensionally-decomposed router for on-chip communication in 3D architectures.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Variation-aware task allocation and scheduling for MPSoC.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects.
Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects, 2007

2006
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Design and Management of 3D Chip Multiprocessors Using Network-in-Memory.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Exploring Fault-Tolerant Network-on-Chip Architectures.
Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN 2006), 2006

2005
Design and analysis of an NoC architecture from performance, reliability and energy perspective.
Proceedings of the 2005 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2005


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