Dong Jiang

Orcid: 0000-0001-5833-241X

Affiliations:
  • South China University of Technology, School of Microelectronics, Guangzhou, China


According to our database1, Dong Jiang authored at least 17 papers between 2020 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
C2-LSM: A Storm-NoC Based Neuromorphic Processor for High-Accuracy Liquid State Machine With Cube-Cluster Topology.
IEEE Trans. Biomed. Circuits Syst., April, 2026

A Multi-Precision Tensor Processing Unit for Accelerating Matrix Computations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
A Spin Scale-Aware Self-Adaptive Ising Annealing Processing Architecture for Combinatorial Optimization Problems.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2025

An SRAM Compute-in-Memory based NTT Accelerator for CRYSTALS-KYBER.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024
DCAP: A Scalable Decoupled-Clustering Annealing Processor for Large-Scale Traveling Salesman Problems.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

Unidirectional and hierarchical on-chip interconnected architecture for large-scale hardware spiking neural networks.
Neurocomputing, 2024

A Parallel Tempering Processing Architecture with Multi-Spin Update for Fully-Connected Ising Models.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Hardware Spiking Neural Networks with Pair-Based STDP Using Stochastic Computing.
Neural Process. Lett., December, 2023

An Ising Model-Based Annealing Processor With 1024 Fully Connected Spins for Combinatorial Optimization Problems.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

A Network-on-Chip-Based Annealing Processing Architecture for Large-Scale Fully Connected Ising Model.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

A Scalable Annealing Processing Architecture for Fully-Connected Ising Models.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

An Annealing Processor based on 1k-Spin Fully-Connected Ising Model for Combinatorial Optimization Problems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Genuine-Equilibrium Monte Carlo Sampling-Based Effective Algorithm for Fully-Connected Ising Models.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

2022
A Fully-Connected and Area-Efficient Ising Model Annealing Accelerator for Combinatorial Optimization Problems.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2021
Minimally buffered deflection router for spiking neural network hardware implementations.
Neural Comput. Appl., 2021

2020
Multi-Ring on-Chip Interconnected Architecture for Spiking Neural Network Hardware Implementations.
Proceedings of the 22nd IEEE International Conference on High Performance Computing and Communications; 18th IEEE International Conference on Smart City; 6th IEEE International Conference on Data Science and Systems, 2020

An Energy-aware Spiking Neural Network Hardware Mapping based on Particle Swarm Optimization and Genetic Algorithm.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2020


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