Enyi Yao

Orcid: 0000-0002-0019-2263

According to our database1, Enyi Yao authored at least 22 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
An Auto Chip Package Surface Defect Detection Based on Deep Learning.
IEEE Trans. Instrum. Meas., 2024

2023
Representation Learning Method for Circular Seal Based on Modified MLP-Mixer.
Entropy, November, 2023

An Ising Model-Based Annealing Processor With 1024 Fully Connected Spins for Combinatorial Optimization Problems.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

A Network-on-Chip-Based Annealing Processing Architecture for Large-Scale Fully Connected Ising Model.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

A Scalable Annealing Processing Architecture for Fully-Connected Ising Models.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

An Annealing Processor based on 1k-Spin Fully-Connected Ising Model for Combinatorial Optimization Problems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Genuine-Equilibrium Monte Carlo Sampling-Based Effective Algorithm for Fully-Connected Ising Models.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

ViT - and LSTM-Based FMCW Radar Target Recognition System.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

2022
Exploring the high-throughput and low-delay hardware design of SM4 on FPGA.
Proceedings of the 19th International SoC Design Conference, 2022

A Fully-Connected and Area-Efficient Ising Model Annealing Accelerator for Combinatorial Optimization Problems.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2021
Detecting LED Chip Surface Defects with Modified Faster R-CNN.
Proceedings of the 18th International SoC Design Conference, 2021

2018
A Novel Low Voltage DCVSL Circuit Design based on Wilson Current Mirror.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
VLSI Extreme Learning Machine: A Design Space Exploration.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Hardware architecture for large parallel array of Random Feature Extractors applied to image recognition.
Neurocomputing, 2017

2016
A 0.7 V, 40 nW Compact, Current-Mode Neural Spike Detector in 65 nm CMOS.
IEEE Trans. Biomed. Circuits Syst., 2016

A 128-Channel Extreme Learning Machine-Based Neural Decoder for Brain Machine Interfaces.
IEEE Trans. Biomed. Circuits Syst., 2016

Pulse-based feature extraction for hardware-efficient neural recording systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
A 1 V, compact, current-mode neural spike detector with detection probability estimator in 65 nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 128 channel 290 GMACs/W machine learning based co-processor for intention decoding in brain machine interfaces.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Random projection for spike sorting: Decoding neural signals the neural network way.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2013
Computation using mismatch: Neuromorphic extreme learning machines.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

2012
A low-power, reconfigurable smart sensor system for EEG acquisition and classification.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012


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