Douglas H. Summerville

According to our database1, Douglas H. Summerville authored at least 26 papers between 1994 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2016
De-encapsulation of network packets for network protocol reverse engineering.
Proceedings of the 2016 IEEE Military Communications Conference, 2016

An Algorithmic Method for the Implantation of Detection-Resistant Covert Hardware Trojans.
Proceedings of the 11th Annual Cyber and Information Security Research Conference, 2016

2015
Ultra-lightweight deep packet anomaly detection for Internet of Things devices.
Proceedings of the 34th IEEE International Performance Computing and Communications Conference, 2015

2013
An optimized reconfigurable power spectral density converter for real-time shrew DDoS attacks detection.
Comput. Electr. Eng., 2013

An optimized design of reconfigurable PSD accelerator for online shrew DDoS attacks detection.
Proceedings of the IEEE INFOCOM 2013, Turin, Italy, April 14-19, 2013, 2013

2012
An extension of RDP code with parallel decoding procedure.
Proceedings of the 2012 IEEE Consumer Communications and Networking Conference (CCNC), 2012

2011
A Survey on the Application of FPGAs for Network Infrastructure Security.
IEEE Commun. Surv. Tutorials, 2011

A fair multi-party non-repudiation scheme for storage clouds.
Proceedings of the 2011 International Conference on Collaboration Technologies and Systems, 2011

Enhancing cloud storage security against roll-back attacks with a new fair multi-party non-repudiation protocol.
Proceedings of the 2011 IEEE Consumer Communications and Networking Conference, 2011

2009
Embedded Systems Interfacing for Engineers using the Freescale HCS08 Microcontroller II: Digital and Analog Hardware Interfacing
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79803-0, 2009

Embedded Systems Interfacing for Engineers using the Freescale HCS08 Microcontroller I: Assembly Language Programming
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79797-2, 2009

Two-stage decomposition of SNORT rules towards efficient hardware implementation.
Proceedings of the 7th International Workshop on Design of Reliable Communication Networks, 2009

2007
Prevention of information attacks by run-time detection of self-replication in computer codes.
J. Comput. Secur., 2007

On Software Implementation of Fast DDP-based Ciphers.
Int. J. Netw. Secur., 2007

2003
Fast software-oriented hash function based on data-dependent lookup operations.
Comput. Sci. J. Moldova, 2003

Detecting Malicious Codes by the Presence of Their "Gene of Self-replication".
Proceedings of the Computer Network Security, 2003

Biological Approach to System Information Security (BASIS): A Multi-agent Approach to Information Security.
Proceedings of the Multi-Agent Systems and Applications III, 2003

2000
An Analysis of Resource Scheduling with Prioritization for QoS in LANs.
Proceedings of the Proceedings 27th Conference on Local Computer Networks, 2000

1998
Executing tree routing algorithms on a high-performance pattern associative router.
J. Syst. Archit., 1998

Approaches for determining dynamic synchronization resource requirements.
Proceedings of the Computers and Their Applications (CATA-98), 1998

1996
A Flexible Bit-Pattern Associative Router for Interconnection Networks.
IEEE Trans. Parallel Distributed Syst., 1996

A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

A Pattern-Associative Router for Interconnection Network Adaptive Algorithms.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

1995
A Pattern-Associative Router for Adaptive Algorithms in Hypercube Networks.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995

1994
A High Performance Pattern Associative Oblivious Router for Tree Topologies.
Proceedings of the 8th International Symposium on Parallel Processing, 1994

A VLSI CAM-based flexible oblivious router for multiprocessor interconnection networks.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994


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