Stamatis Vassiliadis

Microelectron. J., 2009

2008

Regular Expression Matching in Reconfigurable Hardware.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2008

Scalable Multigigabit Pattern Matching for Packet Inspection.

[BibT_eX]

[DOI]

Dionisios N. Pnevmatikatos

IEEE Trans. Very Large Scale Integr. Syst., 2008

Cost-Efficient SHA Hardware Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Test Set Development for Cache Memory in Modern Microprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Implementing the 2-D Wavelet Transform on SIMD-Enhanced General-Purpose Processors.

[BibT_eX]

[DOI]

IEEE Trans. Multim., 2008

Versatility of extended subwords and the matrix register file.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2008

GRAAL: A Framework for Low-Power 3D Graphics Accelerators.

[BibT_eX]

[DOI]

IEEE Computer Graphics and Applications, 2008

Vectorized AES Core for High-throughput Secure Environments.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing for Computational Science, 2008

BRAM-LUT Tradeoff on a Polymorphic DES Design.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2008

Merged Computation for Whirlpool Hashing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

2007

The Molen compiler for reconfigurable processors.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2007

FLUX interconnection networks on demand.

[BibT_eX]

[DOI]

J. Syst. Archit., 2007

Editorial.

[BibT_eX]

[DOI]

J. Syst. Archit., 2007

Editorial.

[BibT_eX]

[DOI]

J. Syst. Archit., 2007

Efficient Multicast Support in High-Speed Packet Switches.

[BibT_eX]

[DOI]

Lotfi Mhamdi

J. Networks, 2007

A reconfigurable platform for multi-service edge routers.

[BibT_eX]

[DOI]

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Design Space Exploration of Configuration Manager for Network Processing Applications.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Trends in Low Power Handset Software Defined Radio.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2007

A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size.

[BibT_eX]

[DOI]

Carlo Galuzzi

Proceedings of the Embedded Computer Systems: Architectures, 2007

High-Bandwidth Address Generation Unit.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2007

Instruction-Level Fault Tolerance Configurability.

[BibT_eX]

[DOI]

Demid Borodin

Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Optimizing Cache Performance of the Discrete Wavelet Transform Using a Visualization Tool.

[BibT_eX]

[DOI]

Jie Tao

Proceedings of the Ninth IEEE International Symposium on Multimedia, 2007

Automated HDL Generation: Comparative Evaluation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Infrastructure for Cross-Layer Designs Interaction.

[BibT_eX]

[DOI]

Zhijiang Chang

Proceedings of the 16th International Conference on Computer Communications and Networks, 2007

Recursive Variable Expansion: A Loop Transformation for Reconfigurable Systems.

[BibT_eX]

[DOI]

Zubair Nawaz

Ozana Silvia Dragomir

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

The Spiral Search: A Linear Complexity Algorithm for the Generation of Convex MIMO Instruction-Set Extensions.

[BibT_eX]

[DOI]

Carlo Galuzzi

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator.

[BibT_eX]

[DOI]

Proceedings of the FPL 2007, 2007

A Load/Store Unit for a Memcpy Hardware Accelerator.

[BibT_eX]

[DOI]

Filipa Duarte

Proceedings of the FPL 2007, 2007

A Quantitative Prediction Model for Hardware/Software Partitioning.

[BibT_eX]

[DOI]

Proceedings of the FPL 2007, 2007

HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation.

[BibT_eX]

[DOI]

Proceedings of the FPL 2007, 2007

SIMD Vectorization of Histogram Functions.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Customizing Reconfigurable On-Chip Crossbar Scheduler.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Reconfigurable Universal Adder.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs.

[BibT_eX]

[DOI]

Jae Young Hur

Proceedings of the Reconfigurable Computing: Architectures, 2007

Systematic Customization of On-Chip Crossbar Interconnects.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2007

A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions.

[BibT_eX]

[DOI]

Carlo Galuzzi

Proceedings of the Reconfigurable Computing: Architectures, 2007

Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2007

A Dynamic Pricing and Bidding Strategy for Autonomous Agents in Grids.

[BibT_eX]

[DOI]

Proceedings of the Agents and Peer-to-Peer Computing, 6th International Workshop, 2007

2006

A Low-Power Multithreaded Processor for Software Defined Radio.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2006

Editorial.

[BibT_eX]

[DOI]

Andy D. Pimentel

J. VLSI Signal Process., 2006

Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2006

Multimedia rectangularly addressable memory.

[BibT_eX]

[DOI]

IEEE Trans. Multim., 2006

Avoiding Conversion and Rearrangement Overhead in SIMD Architectures.

[BibT_eX]

[DOI]

Demid Borodin

Int. J. Parallel Program., 2006

High-performance switching based on buffered crossbar fabrics.

[BibT_eX]

[DOI]

Comput. Networks, 2006

FLUX Networks: Interconnects on Demand.

[BibT_eX]

[DOI]

Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

SAD Prefetching for MPEG4 Using Flux Caches.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2006

Rescheduling for Optimized SHA-1 Calculation.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2006

Performance Evaluation of an Adaptive FPGA for Network Applications.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

Reconfigurable Fabric Interconnects.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on System-on-Chip, 2006

Accelerating Color Space Conversion Using Extended Subwords and the Matrix Register File.

[BibT_eX]

[DOI]

Proceedings of the Eigth IEEE International Symposium on Multimedia (ISM 2006), 2006

Analysis of a reconfigurable network processor.

[BibT_eX]

[DOI]

Christopher Kachris

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Reconfigurable memory based AES co-processor.

[BibT_eX]

[DOI]

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

A hardware cache memcpy accelerator.

[BibT_eX]

[DOI]

Filipa Duarte

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Reconfigurable FLUX networks.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Regular expression matching for reconfigurable packet inspection.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

A Dynamically Reconfigurable Queue Scheduler.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A reconfigurable hardware based embedded scheduler for buffered crossbar switches.

[BibT_eX]

[DOI]

Lotfi Mhamdi

Christopher Kachris

Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

Market-Based Resource Allocation in Grids.

[BibT_eX]

[DOI]

Proceedings of the Second International Conference on e-Science and Grid Technologies (e-Science 2006), 2006

Compiler-driven FPGA-area allocation for reconfigurable computing.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Automatic selection of application-specific instruction-set extensions.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Improving SHA-2 Hardware Implementations.

[BibT_eX]

[DOI]

Proceedings of the Cryptographic Hardware and Embedded Systems, 2006

Improving the memory behavior of vertical filtering in the discrete wavelet transform.

[BibT_eX]

[DOI]

Proceedings of the Third Conference on Computing Frontiers, 2006

Limitations of special-purpose instructions for similarity measurements in media SIMD extensions.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Compilers, 2006

Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

PISC: Polymorphic Instruction Set Computers.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

Packet pre-filtering for network intrusion detection.

[BibT_eX]

[DOI]

Dionisios N. Pnevmatikatos

Vassilis Dimopoulos

Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2006

Design of a web switch in a reconfigurable platform.

[BibT_eX]

[DOI]

Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2006

2005

IEEE-Compliant IDCT on FPGA-Augmented TriMedia.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2005

The CSI multimedia architecture.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Hardwired MPEG-4 repetitive padding.

[BibT_eX]

[DOI]

IEEE Trans. Multim., 2005

Addition Related Arithmetic Operations via Controlled Transport of Charge.

[BibT_eX]

[DOI]

Sorin Dan Cotofana

IEEE Trans. Computers, 2005

Temporal video up-conversion on a next generation media-processor.

[BibT_eX]

Erwin B. Bellers

Johan G. W. M. Janssen

Proceedings of the Signal and Image Processing (SIP 2005), 2005

Interprocedural Optimization for Dynamic Hardware Configurations.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2005

Sandbridge Software Tools.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2005

Flux Caches: What Are They and Are They Useful?

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2005

Reconfigurable Multiple Operation Array.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2005

Motion estimation performance of the TM3270 processor.

[BibT_eX]

[DOI]

Gerrit A. Slavenburg

Jean-Paul van Itegem

Proceedings of the 2005 ACM Symposium on Applied Computing (SAC), 2005

Avoiding data conversions in embedded media processors.

[BibT_eX]

[DOI]

Proceedings of the 2005 ACM Symposium on Applied Computing (SAC), 2005

The TM3270 Media-Processor.

[BibT_eX]

[DOI]

Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005

Resource allocation on the grid: the GRAPPA approach.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Pervasive Services 2005, 2005

The TM3270 Media-Processor Data Cache.

[BibT_eX]

[DOI]

Jean-Paul van Itegem

Hans Van Antwerpen

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

A Reconfigurable Perfect-Hashing Scheme for Packet Inspection.

[BibT_eX]

[DOI]

Dionisios N. Pnevmatikatos

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

64-bit floating-point FPGA matrix multiplication.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Instruction Scheduling for Dynamic Hardware Configurations.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Future wireless convergence platforms.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Matrix register file and extended subwords: two techniques for embedded media processors.

[BibT_eX]

[DOI]

Proceedings of the Second Conference on Computing Frontiers, 2005

Reconfigurable universal SAD-multiplier array.

[BibT_eX]

[DOI]

Proceedings of the Second Conference on Computing Frontiers, 2005

Instruction Set Architecture Enhancements for Video Processing.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

The Midlifekicker Microarchitecture Evaluation Metric.

[BibT_eX]

[DOI]

Leonel Sousa

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

Performance Comparison of SIMD Implementations of the Discrete Wavelet Transform.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

Pel reconstruction on FPGA-augmented TriMedia.

[BibT_eX]

[DOI]

Sorin Dan Cotofana

IEEE Trans. Very Large Scale Integr. Syst., 2004

Multiple-symbol parallel decoding for variable length codes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

The MOLEN Polymorphic Processor.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2004

The Molen Programming Paradigm.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

A Low-Power Multithreaded Processor for Baseband Communication Systems.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

Dynamic Hardware Reconfigurations: Performance Impact for MPEG2.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

The Virtex II Pro<sup>TM</sup> MOLEN Processor.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

Loading rho-µ-Code: Design Considerations.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

High-Level Energy Estimation for ARM-Based SOCs.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

Memory Bandwidth Requirements of Tile-Based Rendering.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

GraalBench: a 3D graphics benchmark suite for mobile phones.

[BibT_eX]

[DOI]

Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004

Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Efficient tile-aware bounding-box overlap test for tile-based rendering.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on System-on-Chip, 2004

Low cost and latency embedded 3D graphics reciprocation.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Sparse Matrix Transpose Unit.

[BibT_eX]

[DOI]

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

The PowerPC Backend Molen Compiler.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

The MOLEN Processor Prototype.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Visual Data Rectangular Memory.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2004 Parallel Processing, 2004

SCISM vs IA-64 Tagging: Differences/Code Density Effects.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2004 Parallel Processing, 2004

A Static Low-Power, High-Performance 32-bit Carry Skip Adder.

[BibT_eX]

[DOI]

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Scene Management Models and Overlap Tests for Tile-Based Rendering.

[BibT_eX]

[DOI]

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

GRAAL - A Development Framework for Embedded Graphics Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Sandblaster low power DSP [parallel DSP arithmetic microarchitecture].

[BibT_eX]

[DOI]

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Efficient Hardware for Antialiasing Coverage Mask Generation.

[BibT_eX]

[DOI]

Proceedings of the 2004 Computer Graphics International (CGI 2004), 16-19 June 2004, 2004

A Low-Power Carry Skip Adder with Fast Saturation.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

Binary Multiplication based on Single Electron Tunneling.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

Polymorphic Processors: How to Expose Arbitrary Hardware Functionality to Programmers.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September, 2004

2003

Microcode Processing: Positioning and Directions.

[BibT_eX]

[DOI]

IEEE Micro, 2003

Implementation of a streaming execution unit.

[BibT_eX]

[DOI]

J. Syst. Archit., 2003

FPGA-Based Variable Length Decoders.

[BibT_eX]

Proceedings of the IFIP VLSI-SoC 2003, 2003

Evaluation Methodology for Single Electron Encoded Threshold Logic Gates.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SOC: From Systems to Chips, 2003

D-SAB: A Sparse Matrix Benchmark Suite.

[BibT_eX]

[DOI]

Pyrrhos Stathis

Proceedings of the Parallel Computing Technologies, 2003

CMOS Implementation of Generalized Threshold Functions.

[BibT_eX]

[DOI]

Marius Padure

Proceedings of the Artificial Neural Nets Problem Solving Methods, 2003

Design and experimental results of a CMOS flip-flop featuring embedded threshold logic.

[BibT_eX]

[DOI]

Marius Padure

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A Hierarchical Sparse Matrix Storage Format for Vector Processors.

[BibT_eX]

[DOI]

Pyrrhos Stathis

Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Compiling for the Molen Programming Paradigm.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Arbitrating Instructions in an pmu-Coded CCM.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Topic Introduction.

[BibT_eX]

[DOI]

Nikitas J. Dimopoulos

Jean-Francois Collard

Arndt Bode

Proceedings of the Euro-Par 2003. Parallel Processing, 2003

Color Space Conversion for MPEG decoding on FPGA-augmented TriMedia Processor.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

2002

Microcoded Reconfigurable Embedded Processors: Current Developments.

[BibT_eX]

[DOI]

Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study.

[BibT_eX]

[DOI]

Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

A 2D Addressing Mode for Multimedia Applications.

[BibT_eX]

[DOI]

Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

A Java-Enabled DSP.

[BibT_eX]

[DOI]

Michael J. Schulte

Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

Unstructured agent matchmaking: experiments in timing and fuzzy matching.

[BibT_eX]

[DOI]

Proceedings of the 2002 ACM Symposium on Applied Computing (SAC), 2002

Architectural Support for 3D Graphics in the Complex Streamed Instruction Set.

[BibT_eX]

Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002

A low-power threshold logic family.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

A full adder implementation using SET based linear threshold gates.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Parallel Multiple-Symbol Variable-Length Decoding.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Reconfigurable repetitive padding unit.

[BibT_eX]

[DOI]

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Field-Programmable Custom Computing Machines - A Taxonomy -.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2002

MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Performance Scalability of Multimedia Instruction Set Extensions.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2002, 2002

A Sum of Absolute Differences Implementation in FPGA Hardware.

[BibT_eX]

[DOI]

Proceedings of the 28th EUROMICRO Conference 2002, 4-6 September 2002, Dortmund, Germany, 2002

A peer-to-peer agent auction.

[BibT_eX]

[DOI]

Proceedings of the First International Joint Conference on Autonomous Agents & Multiagent Systems, 2002

2001

Multimedia Execution Hardware Accelerator.

[BibT_eX]

[DOI]

Edwin A. Hakkennes

J. VLSI Signal Process., 2001

On Chaos and Neural Networks: The Backpropagation Paradigm.

[BibT_eX]

[DOI]

Artif. Intell. Rev., 2001

Coarse Reconfigurable Multimedia Unit Extension.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001

MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

The MOLEN rho-mu-Coded Processor.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2001

An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia.

[BibT_eX]

[DOI]

Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

Topic 15+20: Multimedia and Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2001: Parallel Processing, 2001

Performance of the Complex Streamed Instruction Set on Image Processing Kernels.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2001: Parallel Processing, 2001

Local Distributed Agent Matchmaking.

[BibT_eX]

[DOI]

Proceedings of the Cooperative Information Systems, 9th International Conference, 2001

Matchmaking among minimal agents without a facilitator.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on Autonomous Agents, 2001

Implementation and Evaluation of the Complex Streamed Instruction Set.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 2001

2000

Elementary function generators for neural-network emulators.

[BibT_eX]

[DOI]

Ming Zhang

IEEE Trans. Neural Networks Learn. Syst., 2000

Signed Digit Addition and Related Operations with Threshold Logic.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2000

A look inside the learning process of neural networks.

[BibT_eX]

[DOI]

Complex., 2000

General-Purpose Processor Huffman Encoding Extension.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Information Technology (ITCC 2000), 2000

Multimedia Enhanced General-Purpose Processors.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE International Conference on Multimedia and Expo, 2000

Hashed Addressed Caches for Embedded Pointer Based Codes (Research Note).

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

Parallel Computer Architecture.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

Complex Streamed Instructions: Introduction and Initial Evaluatio.

[BibT_eX]

[DOI]

Edwin A. Hakkennes

Proceedings of the 26th EUROMICRO 2000 Conference, 2000

The ManArray( Embedded Processor Architecture.

[BibT_eX]

[DOI]

Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Counter Based Superscalar Instruction Issuing.

[BibT_eX]

[DOI]

Proceedings of the 26th EUROMICRO 2000 Conference, 2000

The Future of Flexible HW Platform Architectures Panel Discussion.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

1999

A neuro-emulator with embedded capabilities for generalized learning.

[BibT_eX]

[DOI]

Valentine C. Aikens II

J. Syst. Archit., 1999

Serial binary multiplication with feed-forward neural networks.

[BibT_eX]

[DOI]

Neurocomputing, 1999

Vector ISA Extension for Sparse Matrix-Vector Multiplication.

[BibT_eX]

[DOI]

Pyrrhos Stathis

Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

ManArray Processor Interconnection Network: An Introduction.

[BibT_eX]

[DOI]

Nikos Pitsianis

Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

Hardwired Paeth Codec for Portable Network Graphics (PNG).

[BibT_eX]

[DOI]

Edwin A. Hakkennes

Proceedings of the 25th EUROMICRO '99 Conference, 1999

Delft-Java Dynamic Translation.

[BibT_eX]

[DOI]

Proceedings of the 25th EUROMICRO '99 Conference, 1999

1998

Periodic symmetric functions, serial addition, and multiplication with neural networks.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks, 1998

Chaos and Neural Network Learning. Some Observations.

[BibT_eX]

[DOI]

Neural Process. Lett., 1998

Executing tree routing algorithms on a high-performance pattern associative router.

[BibT_eX]

[DOI]

Douglas H. Summerville

J. Syst. Archit., 1998

Java signal processing: FFTs with bytecodes.

[BibT_eX]

[DOI]

Jesse Thilo

Concurr. Pract. Exp., 1998

The Sum-Absolute-Difference Motion Estimation Accelerato.

[BibT_eX]

[DOI]

Proceedings of the 24th EUROMICRO '98 Conference, 1998

DELFT-JAVA Link Translation Buffer.

[BibT_eX]

[DOI]

Proceedings of the 24th EUROMICRO '98 Conference, 1998

On the Design Complexity of the Issue Logic of Superscalar Machines.

[BibT_eX]

[DOI]

Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997

Establishing the Relevancy of the Bookkeeping Libraries to the Functional Testing of Computer Implementations.

[BibT_eX]

[DOI]

IEEE Trans. Knowl. Data Eng., 1997

The Delft-Java Engine: An Introduction.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par '97 Parallel Processing, 1997

1996

delta-Bit serial binary addition with linear threshold networks.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1996

A Flexible Bit-Pattern Associative Router for Interconnection Networks.

[BibT_eX]

[DOI]

Douglas H. Summerville

IEEE Trans. Parallel Distributed Syst., 1996

Sigmoid Generators for Neural Computing Using Piecewise Approximations.

[BibT_eX]

[DOI]

Ming Zhang

IEEE Trans. Computers, 1996

2-1 Additions and Related Arithmetic Operations with Threshold Logic.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1996

Software Reliability Models for Computer Implementations - An Empirical Study.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 1996

Software Metrics and Microcode: A Case Study.

[BibT_eX]

[DOI]

J. Softw. Maintenance Res. Pract., 1996

Precise Interrupts.

[BibT_eX]

[DOI]

Mayan Moudgill

IEEE Micro, 1996

The Performance Potential of Data Dependence Speculation & Collapsing.

[BibT_eX]

[DOI]

Yiannakis Sazeides

James E. Smith

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

A neuro-emulator with learning and virtual emulation capabilities.

[BibT_eX]

[DOI]

Valentine C. Aikens II

Steven M. Barber

Proceedings of International Conference on Neural Networks (ICNN'96), 1996

Serial Binary Addition with Polynominally Bounded Weights.

[BibT_eX]

[DOI]

Proceedings of the Artificial Neural Networks, 1996

1995

On the prediction of computer implementation faults via static error prediction models.

[BibT_eX]

[DOI]

J. Syst. Softw., 1995

The multi-associative branch target buffer: a cost effective BTB mechanism.

[BibT_eX]

[DOI]

Weili Chu

Microprocess. Microprogramming, 1995

Flexible oblivious router architecture.

[BibT_eX]

[DOI]

Joonho Park

IBM J. Res. Dev., 1995

A Neuro-Architecture with Embedded Learning.

[BibT_eX]

Valentine C. Aikens II

Steven M. Barber

Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995

MFAST: a single chip highly parallel image processing architecture.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1995 International Conference on Image Processing, 1995

XOR and backpropagation learning: in and out of the chaos?

[BibT_eX]

[DOI]

Proceedings of the 3rd European Symposium on Artificial Neural Networks, 1995

1994

A Fuzzy Reasoning Database Question Answering System.

[BibT_eX]

[DOI]

IEEE Trans. Knowl. Data Eng., 1994

High-Performance 3-1 Interlock Collapsing ALU's.

[BibT_eX]

[DOI]

James Phillips

IEEE Trans. Computers, 1994

Software metrics for the microcode of computer systems.

[BibT_eX]

[DOI]

J. Syst. Softw., 1994

An investigation of binary CLA and ripple CMOS adder designs.

[BibT_eX]

[DOI]

Chuan-Jen Chang

Microprocess. Microprogramming, 1994

SCISM: A scalable compound instruction set machine.

[BibT_eX]

[DOI]

Bart Blaner

IBM J. Res. Dev., 1994

Design and evaluation of a DAMQ multiprocessor network with self-compacting buffers.

[BibT_eX]

[DOI]

Joonho Park

Brian W. O'Krafka

Proceedings of the Proceedings Supercomputing '94, 1994

A High Performance Pattern Associative Oblivious Router for Tree Topologies.

[BibT_eX]

[DOI]

Douglas H. Summerville

Proceedings of the 8th International Symposium on Parallel Processing, 1994

1993

Interlock Collapsing ALU's.

[BibT_eX]

[DOI]

James Phillips

Bart Blaner

IEEE Trans. Computers, 1993

Spin: the Sequential Pipelined Neuroemulator.

[BibT_eX]

[DOI]

Int. J. Artif. Intell. Tools, 1993

Proof of correctness of high-performance 3-1 interlock collapsing ALUs.

[BibT_eX]

[DOI]

James E. Phillips

IBM J. Res. Dev., 1993

A load-instruction unit for pipelined processors.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 1993

[BibT_eX]

[DOI]

Mayan Moudgill

Keshav Pingali

Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

A massively parallel diagonal-fold array processor.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Application-Specific Array Processors, 1993

1992

Digital neural emulators using tree accumulation and communication structures.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks, 1992

On the attributes of the SCISM organization.

[BibT_eX]

[DOI]

Bart Blaner

SIGARCH Comput. Archit. News, 1992

Instruction-level parallelism from execution interlock collapsing.

[BibT_eX]

[DOI]

Nadeem Malik

SIGARCH Comput. Archit. News, 1992

Semantic Network Architectures: an Evaluation.

[BibT_eX]

[DOI]

Jamshid Goshtasbi

Int. J. Artif. Intell. Tools, 1992

Interlock collapsing ALU for increased instruction-level parallelism.

[BibT_eX]

[DOI]

Nadeem Malik

Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

1991

Hard-Wired Multipliers with Encoded Partial Products.

[BibT_eX]

[DOI]

Eric M. Schwarz

Baik Moon Sung

IEEE Trans. Computers, 1991

SPIN: a sequential pipelined neurocomputer.

[BibT_eX]

[DOI]

Proceedings of the Third International Conference on Tools for Artificial Intelligence, 1991

1989

A General Proof for Overlapped Multiple-Bit Scanning Multiplications.

[BibT_eX]

[DOI]

Eric M. Schwarz

Don J. Hanrahan

IEEE Trans. Computers, 1989

1988

Parallel Encryted Array Multipliers.

[BibT_eX]

[DOI]