José G. Delgado-Frias
Orcid: 0000-0002-7026-9991
According to our database1,
José G. Delgado-Frias
authored at least 106 papers
between 1988 and 2022.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on eecs.wsu.edu
On csauthors.net:
Bibliography
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Computers, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
MWSCAS Guest Editorial Special Issue Based on the 62nd International Midwest Symposium on Circuits and Systems.
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2017
Integr., 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
An implemented, initialization algorithm for many-dimension, Monte Carlo circuit simulations using Spice.
Proceedings of the IEEE 7th Annual Computing and Communication Workshop and Conference, 2017
2016
Autonomous management of a recursive area hierarchy for large scale wireless sensor networks using multiple parents.
Ad Hoc Networks, 2016
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Management of large-scale wireless sensor networks utilizing multi-parent recursive area hierarchies.
Proceedings of the International Green Computing Conference, 2013
2012
Proceedings of the 3rd International Conference on Ambient Systems, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
2010
FPGA schemes for minimizing the power-throughput trade-off in executing the Advanced Encryption Standard algorithm.
J. Syst. Archit., 2010
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Proceedings of the International Green Computing Conference 2010, 2010
2009
Decreasing energy consumption in address decoders by means of selective precharge schemes.
Microelectron. J., 2009
J. Syst. Archit., 2009
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
2008
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance.
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
Performance analysis of multipath transmission over 802.11-based multihop ad hoc networks: a cross-layer perspective.
IET Commun., 2008
Artif. Life Robotics, 2008
High-performance low-power AND and Sense-Amp address decoders with selective precharging.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
FPGA Schemes with Optimized Routing for the Advanced Encryption Standard.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008
2007
IEEE Trans. Parallel Distributed Syst., 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Artif. Life Robotics, 2007
Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 15th IEEE International Conference on Networks, 2007
Proceedings of the Global Communications Conference, 2007
Redundant Array of Independent Fabrics - An Architecture for Next Generation Network.
Proceedings of the Global Communications Conference, 2007
Using a two-timer scheme to detect selfish nodes in mobile ad-hoc networks.
Proceedings of the Sixth IASTED International Conference on Communications, 2007
Using a cache scheme to detect selfish nodes in mobile ad hoc networks.
Proceedings of the Sixth IASTED International Conference on Communications, 2007
A novel compaction scheme for routing tables in TCAM to enhance cache hit rate.
Proceedings of the Sixth IASTED International Conference on Communications, 2007
2006
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
On Throughput of Multipath Data Transmission over Multihop Ad Hoc Networks.
Proceedings of the Sixth IASTED International Multi-Conference on Wireless and Optical Communications: Conference on Communication Systems and Applications, 2006
Proceedings of the 2006 IEEE International Conference on Wireless and Mobile Computing, 2006
Proceedings of the Third Annual IEEE Communications Society on Sensor and Ad Hoc Communications and Networks, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006
Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006
2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme.
Proceedings of the 2005 International Conference on Computer Design, 2005
A Symmetric Differential Clock Generator for Bit-Serial Hardware.
Proceedings of the 2005 International Conference on Computer Design, 2005
DAMQ Self-Compacting Buffer Schemes for Systems with Network-On-Chip.
Proceedings of the 2005 International Conference on Computer Design, 2005
Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS.
Proceedings of the 2005 International Conference on Computer Design, 2005
2004
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004
H-Tree Interconnection Structure for Reconfigurable DSP Hardware.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004
An H-Tree Based Configuration Scheme for Reconfigurable DSP Hardware.
Proceedings of the International Conference on Embedded Systems and Applications, 2004
A Distributed FIFO Scheme for System on Chip Inter-Component Communication.
Proceedings of the International Conference on Embedded Systems and Applications, 2004
2003
A Two-Level Reconfigurable Architecture for Digital Signal Processing.
Proceedings of the International Conference on VLSI, 2003
A Fault-Tolerant Memory-Based Cell for a Reconfigurable DSP Processor.
Proceedings of the International Conference on VLSI, 2003
A Reconfigurable Switch for a DSP Array.
Proceedings of the International Conference on VLSI, 2003
2001
Proceedings of the Information Assurance in Computer Networks: Methods, 2001
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
2000
IEEE Trans. Neural Networks Learn. Syst., 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000
1999
J. Syst. Archit., 1999
1998
J. Syst. Archit., 1998
Cybern. Syst., 1998
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998
Approaches for determining dynamic synchronization resource requirements.
Proceedings of the Computers and Their Applications (CATA-98), 1998
1996
IEEE Trans. Parallel Distributed Syst., 1996
IEEE Trans. Computers, 1996
J. Softw. Maintenance Res. Pract., 1996
Proceedings of International Conference on Neural Networks (ICNN'96), 1996
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996
Proceedings of the Euro-Par '96 Parallel Processing, 1996
1995
Microprocess. Microprogramming, 1995
A Pattern-Associative Router for Adaptive Algorithms in Hypercube Networks.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995
A VLSI-Processing and Communicating Pipelined Tree for Parallel Computing.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995
A Neuro-Architecture with Embedded Learning.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995
1994
Microprocess. Microprogramming, 1994
Proceedings of the Proceedings Supercomputing '94, 1994
Proceedings of the 8th International Symposium on Parallel Processing, 1994
A VLSI CAM-based flexible oblivious router for multiprocessor interconnection networks.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994
1993
Proceedings of the International Conference on Application-Specific Array Processors, 1993
1992
IEEE Trans. Neural Networks, 1992
1991
Proceedings of the Third International Conference on Tools for Artificial Intelligence, 1991
Proceedings of the Third International Conference on Tools for Artificial Intelligence, 1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
1989
Proceedings of the IEEE International Workshop on Tools for Artificial Intelligence: Architectures, 1989
1988
Proceedings of the 2nd international conference on Supercomputing, 1988