Douglas R. Melo

Orcid: 0000-0001-5791-6958

According to our database1, Douglas R. Melo authored at least 18 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Using HARV-SoC for Reliable Sensing Applications in Radiation Harsh Environments.
Proceedings of the 9th International Workshop on Advances in Sensors and Interfaces, 2023

Characterization of a Fault-Tolerant RISC-V System-on-Chip for Space Environments.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Hardening a Real-Time Operating System for a Dependable RISC-V System-on-Chip.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Implementation and Reliability Evaluation of a RISC-V Vector Extension Unit.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

A Low-Cost Hardware Accelerator for CCSDS 123 Lossless Hyperspectral Image Compression.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2022
A Survey of the RISC-V Architecture Software Support.
IEEE Access, 2022

Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-Chip.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021
MPI hardware framework for many-core based embedded systems.
Int. J. Sens. Networks, 2021

Characterization of a RISC-V System-on-Chip under Neutron Radiation.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

2020
A Low-Cost Fault-Tolerant RISC-V Processor for Space Systems.
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

2019
Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design.
Sensors, 2019

Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router.
Proceedings of the IEEE Latin American Test Symposium, 2019

A Low-Cost Hardware Accelerator for CCSDS 123 Predictor in FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Characterization of a RISC-V Microcontroller Through Fault Injection.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

2018
Analysis of LEON3 systems integration for a Network-on-Chip.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

A Hardware Accelerator for Anisotropic Diffusion Filtering in FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2014
XIRU: Interface de Rede Extensível para Integração de Núcleos a uma Rede-em-Chip.
RITA, 2014


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