Dusung Kim

According to our database, Dusung Kim authored at least 6 papers between 2008 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2013

MULTES: Multilevel Temporal-Parallel Event-Driven Simulation.

Dusung Kim, Maciej J. Ciesielski, Seiyang Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2011

A new distributed event-driven gate-level HDL simulation by accurate prediction.

Dusung Kim, Maciej J. Ciesielski, Seiyang Yang

Proceedings of the Design, Automation and Test in Europe, 2011

Temporal parallel simulation: A fast gate-level HDL simulation using higher level models.

Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams.

Daniel Gomez-Prado, Dusung Kim, Maciej J. Ciesielski, Emmanuel Boutillon

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

2008

Temporal parallel gate-level timing simulation.

Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

A fast two-pass HDL simulation with on-demand dump.

Kyuho Shim, Young-Rae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008