Seiyang Yang

According to our database, Seiyang Yang authored at least 11 papers between 1989 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2014

Predictive parallel event-driven HDL simulation with a new powerful prediction strategy.

Seiyang Yang, Jaehoon Han, Doowhan Kwak, Namdo Kim, Daeseo Cha, Junhyuck Park, Jay Kim

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

MULTES: Multilevel Temporal-Parallel Event-Driven Simulation.

Dusung Kim, Maciej J. Ciesielski, Seiyang Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2011

A new distributed event-driven gate-level HDL simulation by accurate prediction.

Dusung Kim, Maciej J. Ciesielski, Seiyang Yang

Proceedings of the Design, Automation and Test in Europe, 2011

Temporal parallel simulation: A fast gate-level HDL simulation using higher level models.

Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang

Proceedings of the Design, Automation and Test in Europe, 2011

2008

Simulation Acceleration with HW Re-Compilation Avoidance.

Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Temporal parallel gate-level timing simulation.

Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

A fast two-pass HDL simulation with on-demand dump.

Kyuho Shim, Young-Rae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2004

A new state assignment technique for testing and low power.

Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski

Proceedings of the 41th Design Automation Conference, 2004

1992

PLADE: a two-stage PLA decomposition.

Maciej J. Ciesielski, Seiyang Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

1991

Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization.

Seiyang Yang, Maciej J. Ciesielski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

1989

PLA decomposition with generalized decoders.

Seiyang Yang, Maciej J. Ciesielski

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989