E. George Walters III

According to our database, E. George Walters III authored at least 9 papers between 2003 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs.

E. George Walters III

Comput., 2016

2015

Linear and Quadratic Interpolators Using Truncated-Matrix Multipliers and Squarers.

E. George Walters III

Comput., 2015

24-bit significand multiplier for FPGA floating-point multiplication.

E. George Walters III

Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014

Optimized cubic chebyshev interpolator for elementary function hardware implementations.

Masoud Sadeghian, James E. Stine, E. George Walters III

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Partial-product generation and addition for multiplication in FPGAs with 6-input LUTs.

E. George Walters III

Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2012

FPGA-accelerated simulation of truncated-matrix multipliers.

E. George Walters III

Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011

Truncated-matrix multipliers with coefficient shifting.

E. George Walters III, Michael J. Schulte

Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2005

Efficient Function Approximation Using Truncated Multipliers and Squarers.

E. George Walters III, Michael J. Schulte

Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2003

Combined Multiplication and Sum-of-Squares Units.

Michael J. Schulte, Louis Marquette, Shankar Krithivasan, E. George Walters III, John Glossner

Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003