Eduard Säckinger

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Bibliography

2012

On the Noise Optimum of FET Broadband Transimpedance Amplifiers.

[BibT_eX]

[DOI]

Eduard Säckinger

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2011

On the Excess Noise Factor Gamma of a FET Driven by a Capacitive Source.

[BibT_eX]

[DOI]

Eduard Säckinger

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010

The Transimpedance Limit.

[BibT_eX]

[DOI]

Eduard Säckinger

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2006

A 5-V AC-Powered CMOS Filter-Selectivity Booster for POTS/ADSL Splitter Size Reduction.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2006

A Multi-Carrier QAM Transceiver for Ultra-Wideband Optical Communication.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2006

A 5V AC-Powered CMOS Filter-Selectivity Booster for POTS/ADSL Splitter Size Reduction.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

An integrated CMOS transceiver for a 40Gb/s SCM optical communication system.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2000

A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers.

[BibT_eX]

[DOI]

Eduard Säckinger

Wilhelm C. Fischer

IEEE J. Solid State Circuits, 2000

A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2000

1999

A 15-mW, 155-Mb/s CMOS burst-mode laser driver with automatic power control and end-of-life detection.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1999

1997

Measurement of Finite-Precision Effects in Handwriting- and Speech-Recognition Algorithms.

[BibT_eX]

[DOI]

Eduard Säckinger

Proceedings of the Artificial Neural Networks, 1997

1996

A board system for high-speed image analysis and neural networks.

[BibT_eX]

[DOI]

Eduard Säckinger

Hans Peter Graf

IEEE Trans. Neural Networks, 1996

Neural Information Processing and VLSI [Book Review].

[BibT_eX]

[DOI]

Eduard Sackinger

IEEE Commun. Mag., 1996

1994

Comparison of classifier methods: a case study in handwritten digit recognition.

[BibT_eX]

[DOI]

Proceedings of the 12th IAPR International Conference on Pattern Recognition, 1994

1993

Recent developments of electronic neural nets in North America.

[BibT_eX]

[DOI]

Hans Peter Graf

Eduard Säckinger

Lawrence D. Jackel

J. VLSI Signal Process., 1993

Signature Verification Using A "Siamese" Time Delay Neural Network.

[BibT_eX]

[DOI]

Int. J. Pattern Recognit. Artif. Intell., 1993

Signature Verification Using a Siamese Time Delay Neural Network.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 6, 1993

1992

Application of the ANNA neural network chip to high-speed character recognition.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks, 1992

Hardware requirements for neural network pattern classifiers: a case study and implementation.

[BibT_eX]

[DOI]

IEEE Micro, 1992

1991

An analog neural network processor with programmable topology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, December, 1991

A Neurocomputer Board Based on the ANNA Neural Network Chip.

[BibT_eX]

[DOI]

Eduard Säckinger

Bernhard E. Boser

Lawrence D. Jackel

Proceedings of the Advances in Neural Information Processing Systems 4, 1991

A neural network approach to handprint character recognition.

[BibT_eX]

[DOI]

Christopher J. C. Burges

Proceedings of the Compcon Spring '91, San Francisco, 1991

1990

A high-swing, high-impedance MOS cascode circuit.

[BibT_eX]

[DOI]

Eduard Sackinger

Walter Guggenbuhl

IEEE J. Solid State Circuits, February, 1990

1988

An analog trimming circuit based on a floating-gate device.

[BibT_eX]

[DOI]

Eduard Sackinger

Walter Guggenbuhl

IEEE J. Solid State Circuits, December, 1988

Eduard Säckinger

Bibliography

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