Edward Gebara

According to our database1, Edward Gebara authored at least 8 papers between 2004 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2019
A Broadband Logarithmic Power Detector Using 130 nm SiGe BiCMOS Technology.
Proceedings of the 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019

2007
A 0.25-um BiCMOS Feed Foward Equalizer Using Active Delay Line for Backplane Communication.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Digitally Controlled 10-Gb/s Adjustable Delay Line for Adaptive Filter Design in standard CMOS Technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A 10-Gb/sec unclocked current-mode logic (CML) analog decision-feedback equalizer (ADFE) in 0.18-μm CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006
A reconfigurable fully-integrated 0.18µm CMOS feed forward equalizer IC for 10-Gb/sec backplane links.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
A Novel Clock Recovery Scheme with Improved Jitter Tolerance for PAM4 Signaling.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

A 0.18µm-CMOS near-end crosstalk (NEXT) noise canceller utilizing tunable active filters for 4-PAM/20Gbps throughput backplane channels.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits.
IEEE J. Solid State Circuits, 2004


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