Soumya Chandramouli

According to our database1, Soumya Chandramouli authored at least 8 papers between 2004 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019

2018
A 56 Gb/s PAM4 receiver with low-overhead threshold and edge-based DFE FIR and IIR-tap adaptation in 65nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2007
A 0.25-um BiCMOS Feed Foward Equalizer Using Active Delay Line for Backplane Communication.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Digitally Controlled 10-Gb/s Adjustable Delay Line for Adaptive Filter Design in standard CMOS Technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A 10-Gb/sec unclocked current-mode logic (CML) analog decision-feedback equalizer (ADFE) in 0.18-μm CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2005
A Novel Clock Recovery Scheme with Improved Jitter Tolerance for PAM4 Signaling.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

A 0.18µm-CMOS near-end crosstalk (NEXT) noise canceller utilizing tunable active filters for 4-PAM/20Gbps throughput backplane channels.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits.
IEEE J. Solid State Circuits, 2004


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