Eero Aho

According to our database, Eero Aho authored at least 17 papers between 2002 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2012

Towards real-time applications in mobile web browsers.

Eero Aho, Kimmo Kuusilinna, Tomi Aarnio, Janne Pietiainen, Jari Nikara

Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012

2011

OpenCL implementation of Cholesky matrix decomposition.

Claudio Brunelli, Eero Aho, Heikki Berg

Proceedings of the 2011 International Symposium on System on Chip, 2011

2009

A Configurable Motion Estimation Architecture for Block-Matching Algorithms.

Jarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen

IEEE Trans. Circuits Syst. Video Technol., 2009

Memory access characteristics of H.264 video encoder on embedded processor.

Eero Aho, Kimmo Kuusilinna, Jari Nikara

Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Performance analysis of multi-channel memories in mobile devices.

Jari Nikara, Eero Aho, Petri A. Tuominen, Kimmo Kuusilinna

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

A case for multi-channel memories in video recording.

Eero Aho, Jari Nikara, Petri A. Tuominen, Kimmo Kuusilinna

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Configurable Data Memory for Multimedia Processing.

Eero Aho, Jarno Vanne, Timo D. Hämäläinen

J. Signal Process. Syst., 2008

A Parallel Memory System for Variable Block-Size Motion Estimation Algorithms.

Jarno Vanne, Eero Aho, Timo D. Hämäläinen, Kimmo Kuusilinna

IEEE Trans. Circuits Syst. Video Technol., 2008

2007

Configurable implementation of parallel memory based real-time video downscaler.

Eero Aho, Jarno Vanne, Timo D. Hämäläinen, Kimmo Kuusilinna

Microprocess. Microsystems, 2007

2006

A High-Performance Sum of Absolute Difference Implementation for Motion Estimation.

Jarno Vanne, Eero Aho, Timo Hämäläinen, Kimmo Kuusilinna

IEEE Trans. Circuits Syst. Video Technol., 2006

Parallel Memory Implementation for Arbitrary Stride Accesses.

Eero Aho, Jarno Vanne, Timo D. Hämäläinen

Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Parallel Memory Architecture for Arbitrary Stride Accesses.

Eero Aho, Jarno Vanne, Timo D. Hämäläinen

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005

Comments on "Winscale: an image-scaling algorithm using an area pixel Model".

Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo D. Hämäläinen

IEEE Trans. Circuits Syst. Video Technol., 2005

Block-level parallel processing for scaling evenly divisible images.

Eero Aho, Jarno Vanne, Timo D. Hämäläinen, Kimmo Kuusilinna

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Block-level parallel processing for scaling evenly divisible frames.

Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo Hämäläinen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Address Computation in Configurable Parallel Memory Architecture.

Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo D. Hämäläinen

IEICE Trans. Inf. Syst., 2004

2002

Enhanced Configurable Parallel Memory Architecture.

Jarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen

Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002