Claudio Brunelli

According to our database1, Claudio Brunelli authored at least 21 papers between 2003 and 2011.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2011
State of the art baseband DSP platforms for Software Defined Radio: A survey.
EURASIP J. Wirel. Commun. Netw., 2011

OpenCL implementation of Cholesky matrix decomposition.
Proceedings of the 2011 International Symposium on System on Chip, 2011

2010
A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations.
J. Syst. Archit., 2010

Implementation and benchmarking of FFT algorithms on multicore platforms.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

Efficient floating-point texture decompression.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

2009
Approximating sine functions using variable-precision Taylor polynomials.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Mapping of the FFT on a reconfigurable architecture targeted to SDR applications.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

2008
Design of hardware accelerators for embedded multimedia applications.
PhD thesis, 2008

Design space exploration of an open-source, IP-reusable, scalable floating-point engine for embedded applications.
J. Syst. Archit., 2008

A coarse-grain reconfigurable architecture for multimedia applications featuring subword computation capabilities.
J. Real Time Image Process., 2008

Implementation of W-CDMA slot synchronization on a reconfigurable System-on-Chip.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

Analyzing models of computation for software defined radio applications.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

Implementation of a floating-point matrix-vector multiplication on a reconfigurable architecture.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Reconfigurable hardware: The holy grail of matching performance with programming productivity.
Proceedings of the FPL 2008, 2008

A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck.
Proceedings of the FPL 2008, 2008

2007
Implementation of a 2D low-pass image filtering algorithm on a reconfigurable device.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

2006
A Coarse-Grain Reconfigurable Machine with Floating-Point Arithmetic Capabilities.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Design And Verification of a VHDL Model of a Floating-Point Unit for a RISC Microprocessor.
Proceedings of the International Symposium on System-on-Chip, 2006

2005
A FPGA Implementation of An Open-Source Floating-Point Computation System.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

2004
A reconfigurable FPU as IP component for SoCs.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

2003
A system level IP integration methodology for fast SOC design.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003


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