Enrico Martinelli

According to our database1, Enrico Martinelli
  • authored at least 29 papers between 1978 and 2013.
  • has a "Dijkstra number"2 of four.

Timeline

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Bibliography

2013
Olympic: A Hierarchical All-Optical Photonic Network for Low-Power Chip Multiprocessors.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2011
A high performance ROM-based structure for modular exponentiation.
Computers & Electrical Engineering, 2011

2009
Instruction Set Extensions for Cryptographic Applications.
Proceedings of the Cryptographic Engineering, 2009

2008
Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2/sup m/).
IEEE Trans. Computers, 2008

2007
Inclusion of a Montgomery Multiplier Unit into an Embedded Processor's Datapath to Speed-up Elliptic Curve Cryptography.
Proceedings of the Third International Symposium on Information Assurance and Security, 2007

2005
NEUROM: a ROM based RNS digital neuron.
Neural Networks, 2005

2004
A workload characterization of elliptic curve cryptography methods in embedded environments.
SIGARCH Computer Architecture News, 2004

WebMIPS: a new web-based MIPS simulation environment for computer architecture education.
Proceedings of the 2004 workshop on Computer architecture education, 2004

A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields.
Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004

2003
How to fake an RSA signature by encoding modular root finding as a SAT problem.
Discrete Applied Mathematics, 2003

2002
Fast modular exponentiation of large numbers with large exponents.
Journal of Systems Architecture, 2002

2001
Adaptive graphical pattern recognition for the classification of company logos.
Pattern Recognition, 2001

2000
Learning User Profiles in NAUTILUS.
Proceedings of the Adaptive Hypermedia and Adaptive Web-Based Systems, 2000

1999
A Voice Device with an Application-Adapted Protocol for Microsoft Windows.
Proceedings of the IEEE International Conference on Multimedia Computing and Systems, 1999

1998
Inductive inference from noisy examples using the hybrid finite state filter.
IEEE Trans. Neural Networks, 1998

Sign detection in residue arithmetic units.
Journal of Systems Architecture, 1998

Logic Design of a Fast Circuit for Iterative Additions in Redundant Hybrid.
Comput. J., 1998

1997
Inductive Inference of Tree Automata by Recursive Neural Networks.
Proceedings of the AI*IA 97: Advances in Artificial Intelligence, 1997

1995
Liquidity management with fuzzy qualitative constraints.
Decision Support Systems, 1995

1993
On the Lower Bound to the VLSI Complexity of Number Conversion from Weighted to Residue Representation.
IEEE Trans. Computers, 1993

1991
A VLSI Modulo m Multiplier.
IEEE Trans. Computers, 1991

A VLSI architecture for RNS with MI adders.
Integration, 1991

1990
A VLSI structure forX(modm) operation.
VLSI Signal Processing, 1990

VLSI Binary-Residue Converters for Pipelined Processing.
Comput. J., 1990

1986
Fast hardware graphic generators of curve families.
Computers & Graphics, 1986

1984
A Fast VLSI Conversion Between Binary and Residue Systems.
Inf. Process. Lett., 1984

A fast near optimum VLSI implementation of FFT using residue number systems.
Integration, 1984

1982
On switching network functionalities and their relationships.
International Journal of Parallel Programming, 1982

1978
LSI components modelling in a three-valued functional simulation.
Proceedings of the 15th Design Automation Conference, 1978


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