Sandro Bartolini

According to our database1, Sandro Bartolini authored at least 34 papers between 2001 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Scalable Path-Setup Scheme for All-Optical Dynamic Circuit Switched NoCs in Cache Coherent CMPs.
JETC, 2018

Augmented Virtuality for Coastal Management: A Holistic Use of In Situ and Remote Sensing for Large Scale Definition of Coastal Dynamics.
ISPRS Int. J. Geo-Information, 2018

Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems.
Future Generation Comp. Syst., 2018

2017
PHAST Library - Enabling Single-Source and High Performance Code for GPUs and Multi-cores.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017

2015
Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects.
Proceedings of the International Conference on Computing, Networking and Communications, 2015

2014
Design Options for Optical Ring Interconnect in Future Client Devices.
JETC, 2014

Managing resources dynamically in hybrid photonic-electronic networks-on-chip.
Concurrency and Computation: Practice and Experience, 2014

Exploiting silicon photonics for energy-efficient heterogeneous parallel architectures.
Concurrency and Computation: Practice and Experience, 2014

Towards compelling cases for the viability of silicon-nanophotonic technology in future manycore systems.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Solving Graph Partitioning Problems Arising in Tagless Cache Management.
Proceedings of the Combinatorial Optimization - Third International Symposium, 2014

Simultaneous Optical Path-Setup for Reconfigurable Photonic Networks in Tiled CMPs.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPs.
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013

Olympic: A Hierarchical All-Optical Photonic Network for Low-Power Chip Multiprocessors.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
A Simple On-Chip Optical Interconnection for Improving Performance of Coherency Traffic in CMPs.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Eighth MEDEA Workshop.
Trans. HiPEAC, 2011

Link-time optimization for power efficiency in a tagless instruction cache.
Proceedings of the CGO 2011, 2011

2010
Feedback-Driven Restructuring of Multi-threaded Applications for NUCA Cache Performance in CMPs.
Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010

2009
Instruction Set Extensions for Cryptographic Applications.
Proceedings of the Cryptographic Engineering, 2009

2008
Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2/sup m/).
IEEE Trans. Computers, 2008

Instruction Cache Energy Saving Through Compiler Way-Placement.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
MEmory performance: DEaling with applications, systems and architecture.
SIGARCH Computer Architecture News, 2007

Inclusion of a Montgomery Multiplier Unit into an Embedded Processor's Datapath to Speed-up Elliptic Curve Cryptography.
Proceedings of the Third International Symposium on Information Assurance and Security, 2007

2006
Memory performance: dealing with applications, systems and architecture.
SIGARCH Computer Architecture News, 2006

Issues in Embedded Single-Chip Multicore Architectures.
J. Embedded Computing, 2006

Embedded processors and systems: Architectural issues and solutions for emerging applications.
J. Embedded Computing, 2006

2005
Optimizing instruction cache performance of embedded systems.
ACM Trans. Embedded Comput. Syst., 2005

Guests editor's introduction.
SIGARCH Computer Architecture News, 2005

2004
A proposal for input-sensitivity analysis of profile-driven optimizations on embedded applications.
SIGARCH Computer Architecture News, 2004

A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields.
Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004

2002
A cache-aware program transformation technique suitable for embedded systems.
Information & Software Technology, 2002

2001
Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction.
SIGARCH Computer Architecture News, 2001

An Object Level Transformation Technique to Improve the Performance of Embedded Applications.
Proceedings of the 1st IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2001), 2001


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