Sandro Bartolini
Orcid: 0000-0002-7975-3632
According to our database1,
Sandro Bartolini
authored at least 50 papers
between 2001 and 2024.
Collaborative distances:
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Bibliography
2024
Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024
2023
IEEE Access, 2023
IEEE Access, 2023
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023
Energy and Performance Improvements for Convolutional Accelerators Using Lightweight Address Translation Support.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
2022
J. Syst. Archit., 2022
Int. J. High Perform. Comput. Appl., 2022
Flexible task-DAG management in PHAST library: Data-parallel tasks and orchestration support for heterogeneous systems.
Concurr. Comput. Pract. Exp., 2022
Concurr. Comput. Pract. Exp., 2022
IEEE Access, 2022
2020
2019
PHAST - A Portable High-Level Modern C++ Programming Library for GPUs and Multi-Cores.
IEEE Trans. Parallel Distributed Syst., 2019
Parallel bitsliced AES through PHAST: a single-source high-performance library for multi-cores and GPUs.
J. Cryptogr. Eng., 2019
Task-DAG Support in Single-Source PHAST Library: Enabling Flexible Assignment of Tasks to CPUs and GPUs in Heterogeneous Architectures.
Proceedings of the 10th International Workshop on Programming Models and Applications for Multicores and Manycores, 2019
2018
Scalable Path-Setup Scheme for All-Optical Dynamic Circuit Switched NoCs in Cache Coherent CMPs.
ACM J. Emerg. Technol. Comput. Syst., 2018
Augmented Virtuality for Coastal Management: A Holistic Use of In Situ and Remote Sensing for Large Scale Definition of Coastal Dynamics.
ISPRS Int. J. Geo Inf., 2018
Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems.
Future Gener. Comput. Syst., 2018
Proceedings of the Cyber-Physical Systems Security., 2018
2017
PHAST Library - Enabling Single-Source and High Performance Code for GPUs and Multi-cores.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017
2015
Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects.
Proceedings of the International Conference on Computing, Networking and Communications, 2015
2014
ACM J. Emerg. Technol. Comput. Syst., 2014
Concurr. Comput. Pract. Exp., 2014
Exploiting silicon photonics for energy-efficient heterogeneous parallel architectures.
Concurr. Comput. Pract. Exp., 2014
Towards compelling cases for the viability of silicon-nanophotonic technology in future manycore systems.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
Proceedings of the Combinatorial Optimization - Third International Symposium, 2014
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014
Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPs.
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013
Olympic: A Hierarchical All-Optical Photonic Network for Low-Power Chip Multiprocessors.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
A Simple On-Chip Optical Interconnection for Improving Performance of Coherency Traffic in CMPs.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
Proceedings of the CGO 2011, 2011
2010
Feedback-Driven Restructuring of Multi-threaded Applications for NUCA Cache Performance in CMPs.
Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010
2009
Proceedings of the Cryptographic Engineering, 2009
2008
Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2<sup>m</sup>).
IEEE Trans. Computers, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
SIGARCH Comput. Archit. News, 2007
Inclusion of a Montgomery Multiplier Unit into an Embedded Processor's Datapath to Speed-up Elliptic Curve Cryptography.
Proceedings of the Third International Symposium on Information Assurance and Security, 2007
2006
SIGARCH Comput. Archit. News, 2006
Embedded processors and systems: Architectural issues and solutions for emerging applications.
J. Embed. Comput., 2006
2005
ACM Trans. Embed. Comput. Syst., 2005
2004
A proposal for input-sensitivity analysis of profile-driven optimizations on embedded applications.
SIGARCH Comput. Archit. News, 2004
A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields.
Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004
2002
Inf. Softw. Technol., 2002
2001
Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction.
SIGARCH Comput. Archit. News, 2001
An Object Level Transformation Technique to Improve the Performance of Embedded Applications.
Proceedings of the 1st IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2001), 2001