Roberto Giorgi

According to our database1, Roberto Giorgi authored at least 65 papers between 1996 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 





Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise - Designing a Computer Architecture via HLS).
Int. J. Reconfigurable Comput., 2019

WebRISC-V: a Web-Based Education-Oriented RISC-V Pipeline Simulation Environment.
Proceedings of the Workshop on Computer Architecture Education, 2019

A Design Space Exploration Tool Set for Future 1K-core High-Performance Computers.
Proceedings of the Rapid Simulation and Performance Evaluation: Methods and Tools, 2019

Analyzing the Impact of Operating System Activity of Different Linux Distributions in a Distributed Environment.
Proceedings of the 27th Euromicro International Conference on Parallel, 2019

AXIOM: A Scalable, Efficient and Reconfigurable Embedded Platform.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Scalable embedded computing through reconfigurable hardware: Comparing DF-Threads, cilk, openmpi and jump.
Microprocess. Microsystems, 2018

Energy Efficiency Exploration on the ZYNQ Ultrascale+.
Proceedings of the 30th International Conference on Microelectronics, 2018

The AXIOM platform for next-generation cyber physical systems.
Microprocess. Microsystems, 2017

Chapter Two - Exploring Future Many-Core Architectures: The TERAFLUX Evaluation Framework.
Adv. Comput., 2017

Rapid prototyping IoT solutions based on Machine Learning.
Proceedings of the European Conference on Cognitive Ergonomics, 2017

Making IoT with UDOO.
IxD&A, 2016

Architectural Support for Fault Tolerance in a Teradevice Dataflow System.
Int. J. Parallel Program., 2016

Exploring dataflow-based thread level parallelism in cyber-physical systems.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Guide to DataFlow Supercomputing - Basic Concepts, Case Studies, and a Detailed Example
Computer Communications and Networks, Springer, ISBN: 978-3-319-16229-4, 2015

Special Section on Terascale Computing.
Future Gener. Comput. Syst., 2015

A scalable thread scheduling co-processor based on data-flow principles.
Future Gener. Comput. Syst., 2015

The AXIOM project (Agile, eXtensible, fast I/O Module).
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing.
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

A matrix multiplier case study for an evaluation of a configurable dataflow-machine.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

Enhancing an x86_64 multi-core architecture with data-flow execution support.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

TERAFLUX: Harnessing dataflow in next generation teradevices.
Microprocess. Microsystems, 2014

An Introduction to DF-Threads and their Execution Model.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing Workshop, 2014

Integration of simulators in virtual 3D computer science classroom.
Proceedings of the 2014 IEEE Global Engineering Education Conference, 2014


Simulating the future kilo-x86-64 core processors and their infrastructure.
Proceedings of the 2012 Spring Simulation Multiconference, 2012

TERAFLUX: exploiting dataflow parallelism in teradevices.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

Embedded reconfigurable architectures.
Proceedings of the 15th International Conference on Compilers, 2012

TERAFLUX: Exploiting Tera-device Computing Challenges.
Proceedings of the 2nd European Future Technologies Conference and Exhibition, 2011

Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture.
Proceedings of the Embedded Computer Systems: Architectures, 2009

Programming Abstractions and Toolchain for Dataflow Multithreading Architectures.
Proceedings of the Eighth International Symposium on Parallel and Distributed Computing, 2009

Exploiting DMA to enable non-blocking execution in Decoupled Threaded Architecture.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Introducing Hardware TLP Support in the Cell Processor.
Proceedings of the 2009 International Conference on Complex, 2009

Instruction Set Extensions for Cryptographic Applications.
Proceedings of the Cryptographic Engineering, 2009

Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2/sup m/).
IEEE Trans. Computers, 2008

Filtering drowsy instruction cache to achieve better efficiency.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Reducing Leakage through Filter Cache.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems.
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007

Memory performance: dealing with applications, systems and architecture.
SIGARCH Computer Architecture News, 2006

Issues in Embedded Single-Chip Multicore Architectures.
J. Embedded Computing, 2006

Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload.
J. Parallel Distributed Comput., 2005

A workload characterization of elliptic curve cryptography methods in embedded environments.
SIGARCH Computer Architecture News, 2004

Speeding-up multiprocessors running DBMS workloads through coherence protocols.
IJHPCN, 2004

WebMIPS: a new web-based MIPS simulation environment for computer architecture education.
Proceedings of the 2004 workshop on Computer architecture education, 2004

A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields.
Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004

Web-based training on computer architecture: the case for JCachesim.
Proceedings of the 2002 workshop on Computer architecture education, 2002

Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture.
Proceedings of the Web Engineering and Peer-to-Peer Computing, 2002

Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation.
IEEE Trans. Computers, 2001

Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction.
SIGARCH Computer Architecture News, 2001

Evaluating Optimizing for Multiprocessors E-Commerce Server Running TPC-W Workload.
Proceedings of the 34th Annual Hawaii International Conference on System Sciences (HICSS-34), 2001

Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications.
Proceedings of the ISCA 14th International Conference on Parallel and Distributed Computing Systems, 2001

Execution and Cache Performance of the Scheduled Dataflow Architecture.
J. UCS, 2000

Performance Analysis of Electronic Commerce Multiprocessor Server.
Proceedings of the 33rd Annual Hawaii International Conference on System Sciences (HICSS-33), 2000

PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors.
IEEE Trans. Parallel Distrib. Syst., 1999

Process Migration Effects on Memory Performance of Multiprocessor.
Proceedings of the High Performance Computing, 1999

An educational environment for designing and performance tuning of embedded systems.
Proceedings of the 1998 workshop on Computer architecture education, 1998

Analysis of Sharing Overhead in Shared Memory Multiprocessors.
Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998

Trace Factory: generating workloads for trace-driven simulation of shared-bus multiprocessors.
IEEE Concurrency, 1997

Cache memory design for embedded systems based on program locality analysis.
Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997

A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors.
Proceedings of the 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 1997

A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors.
Proceedings of the 22rd EUROMICRO Conference '96, 1996