Enrique Cantó

According to our database1, Enrique Cantó
  • authored at least 27 papers between 2004 and 2018.
  • has a "Dijkstra number"2 of five.



In proceedings 
PhD thesis 


On csauthors.net:


Floating-point accelerator for biometric recognition on FPGA embedded systems.
J. Parallel Distrib. Comput., 2018

A new countermeasure against side-channel attacks based on hardware-software co-design.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

Flexible Biometric Online Speaker-Verification System Implemented on FPGA Using Vector Floating-Point Units.
IEEE Trans. VLSI Syst., 2015

Embedded System for Biometric Online Signature Verification.
IEEE Trans. Industrial Informatics, 2014

Real-Time Speaker Verification System Implemented on Reconfigurable Hardware.
Signal Processing Systems, 2013

Fast Self-Reconfigurable Embedded System on Spartan-3.
J. UCS, 2013

Real-time embedded systems powered by FPGA dynamic partial self-reconfiguration: a case study oriented to biometric recognition applications.
J. Real-Time Image Processing, 2013

Guide to FPGA Implementation of Arithmetic Functions
Lecture Notes in Electrical Engineering 149, Springer, ISBN: 978-94-007-2986-5, 2012

Deployment of Run-Time Reconfigurable Hardware Coprocessors Into Compute-Intensive Embedded Applications.
Signal Processing Systems, 2012

FPGA-based Personal Authentication Using Fingerprints.
Signal Processing Systems, 2012

Biometrics-based consumer applications driven by reconfigurable hardware architectures.
Future Generation Comp. Syst., 2012

Run-time self-reconfigurable 2D convolver for adaptive image processing.
Microelectronics Journal, 2011

Hardware-software co-design of an iris recognition algorithm.
IET Information Security, 2011

Fingerprint Image Processing Acceleration Through Run-Time Reconfigurable Hardware.
IEEE Trans. on Circuits and Systems, 2010

SVM speaker verification system based on a low-cost FPGA.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Clock duplicity for high-precision timestamping in Gigabit Ethernet.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Acceleration of complex algorithms on a fast reconfigurable embedded system on Spartan-3.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Self-recofigurable embedded systems on Spartan-3.
Proceedings of the FPL 2008, 2008

Design of a hardware accelerator for fingerprint alignment.
Proceedings of the FPL 2007, 2007

System-on-Chip Design of a Fuzzy Logic Controller Based on Dynamically Reconfigurable Hardware.
ITSSA, 2006

Hardware-Software Co-design of a Dynamically Reconfigurable FPGA-based Fuzzy Logic Controller.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Custom-Made Design of a Digital PID Control System.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

FPGA Implementation of a Ridge Extraction Fingerprint Algorithm Based on Microblaze and Hardware Coprocessor.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Dynamically Reconfigurable CORDIC Coprocessor for Trigonometric.
Proceedings of the ARCS 2006, 2006

Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

Hardware-Software Codesign of a Fingerprint Identification Algorithm.
Proceedings of the Audio- and Video-Based Biometric Person Authentication, 2005

FPGA Implementation of the Ridge Line Following Fingerprint Algorithm.
Proceedings of the Field Programmable Logic and Application, 2004