Gustavo Sutter

According to our database, Gustavo Sutter authored at least 36 papers between 2002 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Enhancing Conditional Stalling to Boost Performance of Stream-Processing Logic With RAW Dependencies.

Tobias Alonso, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara

IEEE Trans. Circuits Syst. II Express Briefs, July, 2023

2021

LOCO-ANS: An Optimization of JPEG-LS Using an Efficient and Low-Complexity Coder Based on ANS.

Tobias Alonso, Gustavo Sutter, Jorge E. López de Vergara

IEEE Access, 2021

2019

Radix-10 decimal logarithm by direct selection for 6-input LUTs programmable devices.

Martín Vázquez, Lucas Leiva, Gustavo Sutter

Microprocess. Microsystems, 2019

Limago: An FPGA-Based Open-Source 100 GbE TCP/IP Stack.

Mario Ruiz, David Sidler, Gustavo Sutter, Gustavo Alonso, Sergio López-Buedo

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018

FPGA-based TCP/IP Checksum Offloading Engine for 100 Gbps Networks.

Gustavo Sutter, Mario Ruiz, Sergio López-Buedo, Gustavo Alonso

Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Submicrosecond Latency Video Compression in a Low-End FPGA-based System-on-Chip.

Tobias Alonso, Mario Ruiz, Angel Lopez Garcia-Arias, Gustavo Sutter, Jorge E. López de Vergara

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017

A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links.

Jose Fernando Zazo, Sergio López-Buedo, Mario Ruiz, Gustavo Sutter

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

An FPGA-based approach for packet deduplication in 100 gigabit-per-second networks.

Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Jose Fernando Zazo, Jorge E. López de Vergara

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

2016

Accurate and affordable packet-train testing systems for multi-gigabit-per-second networks.

Mario Ruiz, Javier Ramos, Gustavo Sutter, Jorge E. López de Vergara, Sergio López-Buedo, Javier Aracil

IEEE Commun. Mag., 2016

Automated synthesis of FPGA-based packet filters for 100 Gbps network monitoring applications.

Jose Fernando Zazo, Sergio López-Buedo, Gustavo Sutter, Javier Aracil

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

FPGA-based encrypted network traffic identification at 100 Gbit/s.

Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Harnessing Programmable SoCs to develop cost-effective network quality monitoring devices.

Mario Ruiz, Javier Ramos, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara, C. Sisterna

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015

Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probes.

Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Javier Ramos, Jorge E. López de Vergara, Javier Aracil

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

2014

Bridging the gap between hardware and software open source network developments.

Marco Forconesi, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara, Javier Aracil

IEEE Netw., 2014

TNT10G: A high-accuracy 10 GbE traffic player and recorder for multi-Terabyte traces.

Jose Fernando Zazo, Marco Forconesi, Sergio López-Buedo, Gustavo Sutter, Javier Aracil

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

2013

Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations.

Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña

IEEE Trans. Ind. Electron., 2013

FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options.

Diego Sanchez-Roman, Victor Moreno, Sergio López-Buedo, Gustavo Sutter, Iván González, Francisco J. Gomez-Arribas, Javier Aracil

J. Syst. Archit., 2013

Accurate and flexible flow-based monitoring for high-speed networks.

Marco Forconesi, Gustavo Sutter, Sergio López-Buedo, Javier Aracil

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012

Guide to FPGA Implementation of Arithmetic Functions

Jean-Pierre Deschamps, Gustavo Sutter, Enrique Cantó

Lecture Notes in Electrical Engineering 149, Springer, ISBN: 978-94-007-2986-5, 2012

Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture.

Iván González, Sergio López-Buedo, Gustavo Sutter, Diego Sanchez-Roman, Francisco J. Gomez-Arribas, Javier Aracil

J. Syst. Archit., 2012

2011

Modular Multiplication and Exponentiation Architectures for Fast RSA Cryptosystem Based on Digit Serial Computation.

Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña

IEEE Trans. Ind. Electron., 2011

Selected Papers from the Southern Programmable Logic Conference (SPL2010).

Elias Todorovich, Gustavo Sutter

Int. J. Reconfigurable Comput., 2011

High-Level Languages and Floating-Point Arithmetic for FPGA-Based CFD Simulations.

Diego Sanchez-Roman, Gustavo Sutter, Sergio López-Buedo, Iván González, Francisco J. Gomez-Arribas, Javier Aracil, Francisco Palacios

IEEE Des. Test Comput., 2011

2010

High-Speed FPGA 10's Complement Adders-Subtractors.

Gery Bioul, Martín Vázquez, Jean-Pierre Deschamps, Gustavo Sutter

Int. J. Reconfigurable Comput., 2010

Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation.

Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009

Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations.

Martín Vázquez, Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

FPGA Implementations of BCD Multipliers.

Gustavo Sutter, Elias Todorovich, Gery Bioul, Martín Vázquez, Jean-Pierre Deschamps

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier.

Carlos Minchola, Gustavo Sutter

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

High speed fixed point dividers for FPGAs.

Gustavo Sutter, Jean-Pierre Deschamps

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008

Selected Papers from SPL 2008: Programmable Logic and Applications.

Gustavo Sutter, Richard Katz

Int. J. Reconfigurable Comput., 2008

2005

Finite Field Division Implementation.

Jean-Pierre Deschamps, Gustavo Sutter

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004

Power Aware Dividers in FPGA.

Gustavo Sutter, Jean-Pierre Deschamps, Gery Bioul, Eduardo I. Boemo

Proceedings of the Integrated Circuit and System Design, 2004

Comparative Study of SRT-Dividers in FPGA.

Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps

Proceedings of the Field Programmable Logic and Application, 2004

2002

Low-Power FSMs in FPGA: Encoding Alternatives.

Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

A Tool for Activity Estimation in FPGAs.

Elias Todorovich, M. Gilabert, Gustavo Sutter, Sergio López-Buedo, Eduardo I. Boemo

Proceedings of the Field-Programmable Logic and Applications, 2002

FSM Decomposition for Low Power in FPGA.

Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo

Proceedings of the Field-Programmable Logic and Applications, 2002