Enrique San Millán
Orcid: 0000-0001-9465-9276
According to our database1,
Enrique San Millán
authored at least 26 papers
between 1999 and 2023.
Collaborative distances:
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Bibliography
2023
Time Synchronization Technique Hardware Implementation for OFDM Systems With Hermitian Symmetry for VLC Applications.
IEEE Access, 2023
2021
Evaluating the computational performance of the Xilinx Ultrascale+ EG Heterogeneous MPSoC.
J. Supercomput., 2021
2018
IEICE Electron. Express, 2018
2017
IEICE Electron. Express, 2017
2016
IEEE Trans. Ind. Informatics, 2016
2015
Fault Attacks on STRNGs: Impact of Glitches, Temperature, and Underpowering on Randomness.
IEEE Trans. Inf. Forensics Secur., 2015
2014
IEEE Trans. Ind. Informatics, 2014
Effect of ionizing radiation on TRNGs for safe telecommunications: Robustness and randomness.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
2011
Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
2010
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the 5th International Conference for Internet Technology and Secured Transactions, 2010
2009
Security Flaws in an Efficient Pseudo-Random Number Generator for Low-Power Environments.
Proceedings of the Security in Emerging Wireless Communication and Networking Systems, 2009
Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
2008
Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
2007
J. Syst. Archit., 2007
Proceedings of the Advances in Biometrics, International Conference, 2007
2003
Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques.
J. Syst. Archit., 2003
2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of ASP-DAC 2001, 2001
1999
Proceedings of the 25th EUROMICRO '99 Conference, 1999
Proceedings of the 1999 Design, 1999