Mario García-Valderas

Orcid: 0000-0003-1615-1607

According to our database1, Mario García-Valderas authored at least 38 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Formal Verification of Fault-Tolerant Hardware Designs.
IEEE Access, 2023

Design Space Analysis for a Digital Lock-In Amplifier for Infrared Gas Sensor Signal Acquisition.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022
Solar Energy Harvesting to Improve Capabilities of Wearable Devices.
Sensors, 2022

Low Power Consumption Online Testing Technique for Wearable Wireless Body Area Networks.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

2020
System Dependability in Edge Computing Wearable Devices.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2019
Assessing SET Sensitivity of Mixed-Signal Circuits at Early Design Stages.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2018
PTM-based hybrid error-detection architecture for ARM microprocessors.
Microelectron. Reliab., 2018

Embedded Emotion Recognition within Cyber-Physical Systems using Physiological Signals.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
On-line testing of sensor networks: A case study.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2014
A method to assess the robustness of cryptographic circuits at the design stage.
Microelectron. J., 2014

Reducing SEU sensitivity in LIN networks: Selective and collaborative hardening techniques.
Proceedings of the 15th Latin American Test Workshop, 2014

Permanent faults on LIN networks: On-line test generation.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Error masking with approximate logic circuits using dynamic probability estimations.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

2012
Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection.
IEEE Trans. Computers, 2012

On the use of embedded debug features for permanent and transient fault resilience in microprocessors.
Microprocess. Microsystems, 2012

Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach.
J. Electron. Test., 2012

Logic masking for SET Mitigation Using Approximate Logic Circuits.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

SEU sensitivity of robust communication protocols.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

2011
Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures.
IEEE Trans. Dependable Secur. Comput., 2011

Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study.
Proceedings of the 12th Latin American Test Workshop, 2011

Evaluation techniques for on-line testing of robust systems based on critical tasks distribution.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

2010
An on-line fault detection technique based on embedded debug features.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

2009
SET Emulation Under a Quantized Delay Model.
J. Electron. Test., 2009

Study of SEU effects in a Turbo Decoder Bit Error Rate.
Proceedings of the 10th Latin American Test Workshop, 2009

Briefing power/reliability optimization in embedded software design.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

In-depth analysis of digital circuits against soft errors for selective hardening.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008
Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

2007
A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

2006
Validation by Fault Injection of a Software Error Detection Technique Dealing with Critical Single Event Upsets.
Proceedings of the 7th Latin American Test Workshop, 2006

Emulation-based Fault Injection in Circuits with Embedded Memories.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Techniques for Fast Transient Fault Grading Based on Autonomous Emulation.
Proceedings of the 2005 Design, 2005

2004
Transient Fault Emulation of Hardened Circuits in FPGA Platforms.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion.
Proceedings of the Field Programmable Logic and Application, 2004

Power Consumption Reduction Through Dynamic Reconfiguration.
Proceedings of the Field Programmable Logic and Application, 2004


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