Luis Entrena

IEEE Trans. Aerosp. Electron. Syst., 2024

2023

Using Approximate Circuits Against Hardware Trojans.

[BibT_eX]

[DOI]

IEEE Des. Test, June, 2023

Formal Verification of Fault-Tolerant Hardware Designs.

[BibT_eX]

[DOI]

Antonio J. Sanchez-Clemente

Roberto Sarmiento

IEEE Access, 2023

Supervised Triple Macrosynchronized Lockstep (STMLS) Architecture for Multicore Processors.

[BibT_eX]

[DOI]

IEEE Access, 2023

2022

Reduced Resolution Redundancy: A Novel Approximate Error Mitigation Technique.

[BibT_eX]

[DOI]

IEEE Access, 2022

Impact of Atmospheric and Space Radiation on Sensitive Electronic Devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2022

2020

A True Random Number Generator Based on Gait Data for the Internet of You.

[BibT_eX]

[DOI]

IEEE Access, 2020

Evaluation of a Reduced Precision Redundancy FFT Design.

[BibT_eX]

[DOI]

Marta Portela

Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2018

Towards a Dependable True Random Number Generator With Self-Repair Capabilities.

[BibT_eX]

[DOI]

Giorgio Di Natale

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

PTM-based hybrid error-detection architecture for ARM microprocessors.

[BibT_eX]

[DOI]

Manuel Peña-Fernandez

S. Philippe

Yolanda Morilla

Pedro Martín-Holgado

Microelectron. Reliab., 2018

Dynamic control of entropy and power consumption in TRNGs for IoT applications.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2018

On the Entropy of Oscillator-Based True Random Number Generators under Ionizing Radiation.

[BibT_eX]

[DOI]

Entropy, 2018

A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide Obfuscation.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Approximate TMR for selective error mitigation in FPGAs based on testability analysis.

[BibT_eX]

[DOI]

Fernanda Lima Kastensmidt

Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018

2016

Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches.

[BibT_eX]

[DOI]

Radek Hrbacek

Lukás Sekanina

IEEE Trans. Reliab., 2016

A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications.

[BibT_eX]

[DOI]

Antonio Martínez-Álvarez

Felipe Restrepo-Calle

IEEE Trans. Dependable Secur. Comput., 2016

Online Test of Control Flow Errors: A New Debug Interface-Based Approach.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

2014

A method to assess the robustness of cryptographic circuits at the design stage.

[BibT_eX]

[DOI]

M. Arévalo-Garbayo

Microelectron. J., 2014

Error masking with approximate logic circuits using dynamic probability estimations.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

A new solution to on-line detection of Control Flow Errors.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

2013

Fast fault injection techniques using FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 14th Latin American Test Workshop, 2013

Exploiting the debug interface to support on-line test of control flow errors.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

2012

Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection.

[BibT_eX]

[DOI]

Raúl Fernández Cardenal

IEEE Trans. Computers, 2012

On the use of embedded debug features for permanent and transient fault resilience in microprocessors.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2012

Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach.

[BibT_eX]

[DOI]

Letícia Maria Bolzani Poehls

N. Marroni

Bernardo Pianta

Fabian Vargas

J. Electron. Test., 2012

Logic masking for SET Mitigation Using Approximate Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

SEU sensitivity of robust communication protocols.

[BibT_eX]

[DOI]

Joaquín Rivas-Abalo

Alberto Martín-Ortega

Javier Martinez-Oter

S. Rodriguez-Bustabad

Ignacio Arruego

Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

2011

Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures.

[BibT_eX]

[DOI]

IEEE Trans. Dependable Secur. Comput., 2011

Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study.

[BibT_eX]

[DOI]

Letícia Maria Bolzani Poehls

Bernardo Pianta

Fabian Vargas

Proceedings of the 12th Latin American Test Workshop, 2011

Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Evaluation techniques for on-line testing of robust systems based on critical tasks distribution.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

AKARI-X: A pseudorandom number generator for secure lightweight systems.

[BibT_eX]

[DOI]

Julio César Hernández Castro

Pedro Peris-Lopez

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

2010

Robust cryptographic ciphers with on-line statistical properties validation.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

An on-line fault detection technique based on embedded debug features.

[BibT_eX]

[DOI]

Michelangelo Grosso

Matteo Sonza Reorda

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Cryptographically secure pseudo-random bit generator for RFID tags.

[BibT_eX]

[DOI]

Pedro Peris-Lopez

Jan C. A. van der Lubbe

Proceedings of the 5th International Conference for Internet Technology and Secured Transactions, 2010

2009

SET Emulation Under a Quantized Delay Model.

[BibT_eX]

[DOI]

Raúl Fernández Cardenal

J. Electron. Test., 2009

Study of SEU effects in a Turbo Decoder Bit Error Rate.

[BibT_eX]

[DOI]

Proceedings of the 10th Latin American Test Workshop, 2009

Briefing power/reliability optimization in embedded software design.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

In-depth analysis of digital circuits against soft errors for selective hardening.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008

Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

Logic Transformations by Multiple Wire Network Addition.

[BibT_eX]

[DOI]

José Alberto Espejo

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007

Low power data processing system with self-reconfigurable architecture.

[BibT_eX]

[DOI]

J. Syst. Archit., 2007

High performance FPGA-based image correlation.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2007

A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Correlation-Based Fingerprint Matching with Orientation Field Alignment.

[BibT_eX]

[DOI]

Proceedings of the Advances in Biometrics, International Conference, 2007

Wavelet-Based Fingerprint Region Selection.

[BibT_eX]

[DOI]

Judith Liu-Jimenez

Proceedings of the Computer Analysis of Images and Patterns, 12th International Conference, 2007

2006

Emulation-based Fault Injection in Circuits with Embedded Memories.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Fault Injection-based Reliability Evaluation of SoPCs.

[BibT_eX]

[DOI]

Proceedings of the 11th European Test Symposium, 2006

An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005

Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Correlation-Based Fingerprint Matching Using FPGAs.

[BibT_eX]

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Techniques for Fast Transient Fault Grading Based on Autonomous Emulation.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

2004

Transient Fault Emulation of Hardened Circuits in FPGA Platforms.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Power Consumption Reduction Through Dynamic Reconfiguration.

[BibT_eX]

[DOI]

Michael G. Lorenz

Luis Mengibar

Proceedings of the Field Programmable Logic and Application, 2004

FPGA Implementation of Biometric Authentication System Based on Hand Geometry.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

Architectures for Biometric Match-on-Token Solutions.

[BibT_eX]

[DOI]

Raul Sánchez-Reillo

Judith Liu-Jimenez

Proceedings of the Biometric Authentication, 2004

2003

Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques.

[BibT_eX]

[DOI]

J. Syst. Archit., 2003

State Encoding for Low-Power FSMs in FPGA.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2003

Data Processing System With Self-reconfigurable Architecture, for Low Cost, Low Power Applications.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002

An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Analysis of the Equivalences and Dominances of Transient Faults at the RT Level.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

New Techniques for Speeding-Up Fault-Injection Campaigns.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

2001

Logic Optimization of Unidirectional Circuits with Structural Methods.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Automatic Insertion of Fault-Tolerant Structures at the RT Level.

[BibT_eX]

[DOI]

Celia López

Emilio Olías

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits.

[BibT_eX]

[DOI]

José Alberto Espejo

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization.

[BibT_eX]

[DOI]

José Alberto Espejo

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Generalized reasoning scheme for redundancy addition and removal logic optimization.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Functional extension of structural logic optimization techniques.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

1999

Logic Restructuring for MUX-Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 25th EUROMICRO '99 Conference, 1999

Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

1996

Timing optimization by an improved redundancy addition and removal technique.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1996

1995

Combinational and sequential logic optimization by redundancy addition and removal.

[BibT_eX]

[DOI]

Kwang-Ting Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

VHDL virtual prototyping.

[BibT_eX]

[DOI]

Serafín Olcoz

Luis Berrojo

Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP '95), 1995

An effective system development environment based on VHDL prototyping.

[BibT_eX]

[DOI]

Serafín Olcoz

Luis Berrojo

Proceedings of the Proceedings EURO-DAC'95, 1995

1993

Sequential logic optimization by redundancy addition and removal.

[BibT_eX]

[DOI]