According to our database1, Eric Stotzer authored at least 15 papers between 1999 and 2014.
Legend:Book In proceedings Article PhD thesis Other
Implementation and Optimization of the OpenMP Accelerator Model for the TI Keystone II Architecture.
Proceedings of the Using and Improving OpenMP for Devices, Tasks, and More, 2014
Exploiting DMA for Performance and Energy Optimized STREAM on a DSP.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
OpenMP on the Low-Power TI Keystone II ARM/DSP System-on-Chip.
Proceedings of the OpenMP in the Era of Low Power Devices and Accelerators, 2013
Co-design of Compiler and Hardware Techniques to Reduce Program Code Size on a VLIW Processor.
CLEI Electron. J., 2012
Unleashing the high-performance and low-power of multi-core DSPs for general-purpose HPC.
Proceedings of the SC Conference on High Performance Computing Networking, 2012
Level-3 BLAS on the TI C6678 Multi-core DSP.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012
OpenMP for Accelerators.
Proceedings of the OpenMP in the Petascale Era - 7th International Workshop on OpenMP, 2011
Prototyping and Programming Tightly Coupled Accelerators.
Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009
Modulo scheduling without overlapped lifetimes.
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, 2009
Implementing OpenMP on a high performance embedded multicore MPSoC.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009
Proceedings of the Euro-Par 2009 Parallel Processing, 2009
Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008
Affinity-based cluster assignment for unrolled loops.
Proceedings of the 16th international conference on Supercomputing, 2002
Software Pipelining Irregular Loops on the TMS320C6000 VLIW DSP Architecture.
Proceedings of The Workshop on Languages, 2001
Modulo Scheduling for the TMS320C6x VLIW DSP Architecture.
Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, 1999