Bart Kienhuis

According to our database1, Bart Kienhuis authored at least 45 papers between 1997 and 2016.

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Bibliography

2016
Determining Performance Boundaries on High-Level System Specifications.
Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016

Parametrized system level design: Real-time X-Ray image processing case study.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2013
HEAP: A Highly Efficient Adaptive multi-Processor framework.
Microprocess. Microsystems, 2013

2012
FIFO Exploration in Mapping Streaming Applications onto the TI OMAP3530 Platform: Case Study and Optimizations.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

Scaling Data-Intensive Applications on Heterogeneous Platforms with Accelerators.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Enabling Automatic Pipeline Utilization Improvement in Polyhedral Process Network Implementations.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011
KPN2GPU: an approach for discovery and exploitation of fine-grain data parallelism in process networks.
SIGARCH Comput. Archit. News, 2011

A data parallel view on polyhedral process networks.
Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems, 2011

High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

IP-XACT extensions for Reconfigurable Computing.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2010
Cool MPSoC programming.
Proceedings of the Design, Automation and Test in Europe, 2010

Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systems.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Introduction.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009

Automated synthesis of streaming C applications to process networks in hardware.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Deriving efficient control in Process Networks with Compaan/Laura.
Int. J. Embed. Syst., 2008

Hierarchical run time deadlock detection in process networks.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

2007
Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation.
IEEE Trans. Signal Process., 2007

Classifying interprocess communication in process network representation of nested-loop programs.
ACM Trans. Embed. Comput. Syst., 2007

Automatic partitioning and mapping of stream-based applications onto the Intel IXP Network processor.
Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, 2007

Interactive presentation: A process splitting transformation for Kahn process networks.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2005
Solving Out-of-Order Communication in Kahn Process Networks.
J. VLSI Signal Process., 2005

Communication Synthesis in a multiprocessor environment.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Expression Synthesis in Process Networks generated by LAURA.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
An Integer Linear Programming Approach to Classify the Communication in Process Networks.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

Increasing Pipelined IP Core Utilization in Process Networks Using Exploration.
Proceedings of the Field Programmable Logic and Application, 2004

Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing.
Proceedings of the 2004 Design, 2004

System Design Using Kahn Process Networks: The Compaan/Laura Approach.
Proceedings of the 2004 Design, 2004

Translating affine nested-loop programs to process networks.
Proceedings of the 2004 International Conference on Compilers, 2004

A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing.
Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003
Modeling Stream-Based Applications Using the SBF Model of Computation.
J. VLSI Signal Process., 2003

Laura: Leiden Architecture Research and Exploration Tool.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Storage Management in Process Networks using the Lexicographically Maximal Preimage.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002
Compilation From Matlab to Process Networks Realized in FPGA.
Des. Autom. Embed. Syst., 2002

Preface.
Des. Autom. Embed. Syst., 2002

A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

Translating Imperative Affine Nested Loop Programs into Process Networks.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

Algorithmic transformation techniques for efficient exploration of alternative application instances.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2000
Deriving Process Networks from Nested Loop Algorithms.
Parallel Process. Lett., 2000

Compaan: deriving process networks from Matlab for embedded signal processing architectures.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

High Level Modeling for Parallel Executions of Nested Loop Algorithms.
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999
A Clustering Approach to Explore Grain-Sizes in the Definition of Processing Elements in Dataflow Architectures.
J. VLSI Signal Process., 1999

1998
The construction of a retargetable simulator for an architecture template.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

1997
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997


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