Oscar G. Plata

According to our database1, Oscar G. Plata authored at least 79 papers between 1989 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2020
Accelerating Sequence Alignments Based on FM-Index Using the Intel KNL Processor.
IEEE ACM Trans. Comput. Biol. Bioinform., 2020

Energy-Efficient Time Series Analysis Using Transprecision Computing.
Proceedings of the 32nd IEEE International Symposium on Computer Architecture and High Performance Computing, 2020

NATSA: A Near-Data Processing Accelerator for Time Series Analysis.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019
Toward a software transactional memory for heterogeneous CPU-GPU processors.
J. Supercomput., 2019

Accelerating time series motif discovery in the Intel Xeon Phi KNL processor.
J. Supercomput., 2019

Improving hardware transactional memory parallelization of computational geometry algorithms using privatizing transactions.
J. Parallel Distributed Comput., 2019

Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding.
Proceedings of the Data Compression Conference, 2019

2018
Privatizing transactions for Lee's algorithm in commercial hardware transactional memory.
J. Supercomput., 2018

Lightweight Hardware Transactional Memory for GPU Scratchpad Memory.
IEEE Trans. Computers, 2018

TMbarrier: Speculative Barriers Using Hardware Transactional Memory.
Proceedings of the 26th Euromicro International Conference on Parallel, 2018

2017
Lazy Irrevocability for Best-Effort Transactional Memory Systems.
IEEE Trans. Parallel Distributed Syst., 2017

Leveraging irrevocability to deal with signature saturation in hardware transactional memory.
J. Supercomput., 2017

Enhancing scalability in best-effort hardware transactional memory systems.
J. Parallel Distributed Comput., 2017

ReduxSTM: Optimizing STM designs for Irregular Applications.
J. Parallel Distributed Comput., 2017

Towards a Software Transactional Memory for Heterogeneous CPU-GPU Processors.
Proceedings of the Parallel Computing is Everywhere, 2017

Hardware Support for Scratchpad Memory Transactions on GPU Architectures.
Proceedings of the Euro-Par 2017: Parallel Processing - 23rd International Conference on Parallel and Distributed Computing, Santiago de Compostela, Spain, August 28, 2017

2016
A comparative analysis of STM approaches to reduction operations in irregular applications.
J. Comput. Sci., 2016

Insights into the Fallback Path of Best-Effort Hardware Transactional Memory Systems.
Proceedings of the Euro-Par 2016: Parallel Processing, 2016

2015
Improving Transactional Memory Performance for Irregular Applications.
Proceedings of the International Conference on Computational Science, 2015

Conflict Detection in Hardware Transactional Memory.
Proceedings of the Transactional Memory. Foundations, Algorithms, Tools, and Applications, 2015

2014
Effective Transactional Memory Execution Management for Improved Concurrency.
ACM Trans. Archit. Code Optim., 2014

Multicore cache hierarchies: design and programmability issues.
Concurr. Comput. Pract. Exp., 2014

Improving Signature Behavior by Irrevocability in Transactional Memory Systems.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Scalability Analysis of Signatures in Transactional Memory Systems.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

2013
Hardware Signature Designs to Deal with Asymmetry in Transactional Data Sets.
IEEE Trans. Parallel Distributed Syst., 2013

LS-Sig: Locality-Sensitive Signatures for Transactional Memory.
IEEE Trans. Computers, 2013

Dealing with Reduction Operations Using Transactional Memory.
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013

Parallelizing the Sparse Matrix Transposition: Reducing the Programmer Effort Using Transactional Memory.
Proceedings of the International Conference on Computational Science, 2013

Exploring Irregular Reduction Support in Transactional Memory.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2013

2012
VLBI-resolution radio-map algorithms: Performance analysis of different levels of data-sharing on multi-socket, multi-core architectures.
Comput. Phys. Commun., 2012

2011
Multiset signatures for transactional memory.
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Spectral evolution simulation on leading multi-socket, multicore platforms.
Proceedings of the 18th International Conference on High Performance Computing, 2011

Unified Locality-Sensitive Signatures for Transactional Memory.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

2010
Interval Filter: A Locality-Aware Alternative to Bloom Filters for Hardware Membership Queries by Interval Classification.
Proceedings of the Intelligent Data Engineering and Automated Learning, 2010

2009
Experiences with Mapping Non-linear Memory Access Patterns into GPUs.
Proceedings of the Computational Science, 2009

Introduction.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009

Improving Signatures by Locality Exploitation for Transactional Memory.
Proceedings of the PACT 2009, 2009

2008
Teaching the Cache Memory System Using a Reconfigurable Approach.
IEEE Trans. Educ., 2008

An analytical model of locality-based parallel irregular reductions.
Parallel Comput., 2008

Using Padding to Optimize Locality in Scientific Applications.
Proceedings of the Computational Science, 2008

2007
Maximum and Sorted Cache Occupation Using Array Padding.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

A New Parallel Sorting Algorithm based on Odd-Even Mergesort.
Proceedings of the 15th Euromicro International Conference on Parallel, 2007

Simulating a Reconfigurable Cache System for Teaching Purposes.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

2006
Topic 4: Compilers for High Performance.
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

2005
On the parallelization of irregular and dynamic programs.
Parallel Comput., 2005

Parallel techniques in irregular codes: cloth simulation as case of study.
J. Parallel Distributed Comput., 2005

Distributed Architecture System for Computer Performance Testing.
Proceedings of the Parallel Processing and Applied Mathematics, 2005

Reducing Cache Misses by Loop Reordering.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005

2004
Parallelization issues of a code for physically-based simulation of fabrics.
Comput. Phys. Commun., 2004

Data partitioning-based parallel irregular reductions.
Concurr. Comput. Pract. Exp., 2004

Optimization Techniques for Irregular and Pointer-Based Programs.
Proceedings of the 12th Euromicro Workshop on Parallel, 2004

A New Dependence Test Based on Shape Analysis for Pointer-Based Codes.
Proceedings of the Languages and Compilers for High Performance Computing, 2004

Applying Loop Tiling and Unrolling to a Sparse Kernel Code.
Proceedings of the Computational Science, 2004

Topic 11: Numerical Algorithms.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

2003
Optimization techniques for parallel irregular reductions.
J. Syst. Archit., 2003

2002
On Improving the Performance of Data Partitioning Oriented Parallel Irregular Reductions.
Proceedings of the 10th Euromicro Workshop on Parallel, 2002

2001
A Data-Parallel Formulation for Divide and Conquer Algorithms.
Comput. J., 2001

Improving parallel irregular reductions using partial array expansion.
Proceedings of the 2001 ACM/IEEE conference on Supercomputing, 2001

Balanced, Locality-Based Parallel Irregular Reductions.
Proceedings of the Languages and Compilers for Parallel Computing, 2001

2000
Automatic parallelization of irregular applications.
Parallel Comput., 2000

A Data Parallel Formulation of the Barnes-Hut Method for N -Body Simulations.
Proceedings of the Applied Parallel Computing, 2000

A compiler method for the parallel execution of irregular reductions in scalable shared memory multiprocessors.
Proceedings of the 14th international conference on Supercomputing, 2000

1999
An Efficient Architecture for the In-Place Fast Cosine Transform.
J. VLSI Signal Process., 1999

Data-parallel support for numerical irregular problems.
Parallel Comput., 1999

On Automatic Parallelization of Irregular Reductions on Scalable Shared Memory Systems.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998
HPF-2 Support for Dynamic Sparse Computations.
Proceedings of the Languages and Compilers for Parallel Computing, 1998

1997
Unified Framework for the Parallelization of Divide and Conquer Based Tridiagonal Systems.
Parallel Comput., 1997

Modelling Superlinear Speedup on Distributed Memory Multiprocessors.
Proceedings of the Parallel Computing: Fundamentals, 1997

An efficient architecture for the in place fast cosine transform.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1995
Image Template Matching on Distributed Memory and Vector Multiprocessors.
Proceedings of the Parallel Computing: State-of-the-Art and Perspectives, 1995

1994
Combining static and dynamic scheduling on distributed-memory multiprocessors.
Proceedings of the 8th international conference on Supercomputing, 1994

Adapting PICL and ParaGraph Tools to Transputer-Based Multicomputers.
Proceedings of the High-Performance Computing and Networking, 1994

Vectorization of the Radix r Self-Sorting FFT.
Proceedings of the Parallel Processing: CONPAR 94, 1994

1993
An Efficient Processor Allocation for Nested Parallel Loops on Distributed Memory Hypercubes.
Parallel Process. Lett., 1993

1992
Design of parallel algorithms for a distributed memory hypercube.
Microprocess. Microsystems, 1992

1991
Modified Gram-Schmidt QR Factorization on Hypercube SIMD Computers.
J. Parallel Distributed Comput., 1991

1990
Image template matching on hypercube SIMD computers.
Signal Process., 1990

ACLE: A Software Package for SIMD Computer Simulation.
Comput. J., 1990

1989
Parallel fuzzy clustering on fixed size hypercube SIMD computers.
Parallel Comput., 1989


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