Erik G. Hallnor

According to our database, Erik G. Hallnor authored at least 6 papers between 2000 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

Haswell: The Fourth-Generation Intel Core Processor.

Per Hammarlund, Alberto J. Martinez, Atiq A. Bajwa, David L. Hill, Erik G. Hallnor, Hong Jiang, Martin G. Dixon, Michael Derr, Mikal Hunsaker, Rajesh Kumar, Randy B. Osborne, Ravi Rajwar, Ronak Singhal, Reynold D'Sa, Robert Chappell, Shiv Kaushik, Srinivas Chennupaty, Stéphan Jourdan, Steve Gunther, Thomas Piazza, Ted Burton

IEEE Micro, 2014

2010

Boomerang: Reducing Power Consumption of Response Packets in NoCs with Minimal Performance Impact.

Zhen Fang, Erik G. Hallnor, Bin Li, Mike Leddige, Seung Eun Lee, Donglai Dai, Srihari Makineni

IEEE Comput. Archit. Lett., 2010

2005

Design and applications of an indirection-based cache structure.

Erik G. Hallnor

PhD thesis, 2005

A Unified Compressed Memory Hierarchy.

Erik G. Hallnor, Steven K. Reinhardt

Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

2004

A compressed memory hierarchy using an indirect index cache.

Erik G. Hallnor, Steven K. Reinhardt

Proceedings of the 3rd Workshop on Memory Performance Issues, 2004

2000

A fully associative software-managed cache design.

Erik G. Hallnor, Steven K. Reinhardt

Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000