Stéphan Jourdan

According to our database, Stéphan Jourdan authored at least 15 papers between 1995 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2014

Haswell: The Fourth-Generation Intel Core Processor.

Per Hammarlund, Alberto J. Martinez, Atiq A. Bajwa, David L. Hill, Erik G. Hallnor, Hong Jiang, Martin G. Dixon, Michael Derr, Mikal Hunsaker, Rajesh Kumar, Randy B. Osborne, Ravi Rajwar, Ronak Singhal, Reynold D'Sa, Robert Chappell, Shiv Kaushik, Srinivas Chennupaty, Stéphan Jourdan, Steve Gunther, Thomas Piazza, Ted Burton

IEEE Micro, 2014

2009

Transitioning the Intel® next generation microarchitectures (nehalem and westmere) into the mainstream.

Lily Pao Looi, Stéphan Jourdan

Proceedings of the 2009 IEEE Hot Chips 21 Symposium (HCS), 2009

2002

A stateless, content-directed data prefetching mechanism.

Robert Cooksey, Stéphan Jourdan, Dirk Grunwald

Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), 2002

2001

An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors.

Pierre Michaud, André Seznec, Stéphan Jourdan

Int. J. Parallel Program., 2001

2000

Early load address resolution via register tracking.

Michael Bekerman, Adi Yoaz, Freddy Gabbay, Stéphan Jourdan, Maxim Kalaev, Ronny Ronen

Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

eXtended Block Cache.

Stéphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen

Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

1999

Speculation Techniques for Improving Load Related Instruction Scheduling.

Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan Jourdan

Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

Correlated Load-Address Predictors.

Michael Bekerman, Stéphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri C. Weiser

Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors.

Pierre Michaud, André Seznec, Stéphan Jourdan

Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999

1998

A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification.

Stéphan Jourdan, Ronny Ronen, Michael Bekerman, Bishara Shomar, Adi Yoaz

Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998

1997

Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution.

Stéphan Jourdan, Jared Stark, Tse-Hao Hsing, Yale N. Patt

Int. J. Parallel Program., 1997

1996

Multiple-Block Ahead Branch Predictors.

André Seznec, Stéphan Jourdan, Pascal Sainrat, Pierre Michaud

Proceedings of the ASPLOS-VII Proceedings, 1996

The effects of mispredicted-path execution on branch prediction structures.

Stéphan Jourdan, Tse-Hao Hsing, Jared Stark, Yale N. Patt

Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996

1995

An investigation of the performance of various instruction-issue buffer topologies.

Stéphan Jourdan, Pascal Sainrat, Daniel Litaize

Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor.

Stéphan Jourdan, Pascal Sainrat, Daniel Litaize

Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995