Esther Y. Cheng

According to our database1, Esther Y. Cheng authored at least 2 papers between 2002 and 2003.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2003
A hierarchical three-way interconnect architecture for hexagonal processors.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

2002
Balancing the Interconnect Topology for Arrays of Processors between Cost and Power.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002


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