Chung-Kuan Cheng

According to our database1, Chung-Kuan Cheng authored at least 265 papers between 1984 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Awards

IEEE Fellow

IEEE Fellow 2000, "For contributions to circuit partitioning and physical layout automation.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2020
Empirical study on sufficient numbers of minimum cuts in strongly connected directed random graphs.
Networks, 2020

Arnoldi algorithms with structured orthogonalization.
CoRR, 2020

R-peak Detection Using a Hybrid of Gaussian and Threshold Sensitivity.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020

Arrhythmia Classification using Deep Learning and Machine Learning with Features Extracted from Waveform-based Signal Processing.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020

SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Three-dimensional Floorplan Representations by Using Corner Links and Partial Order.
ACM Trans. Design Autom. Electr. Syst., 2019

RePlAce: Advancing Solution Quality and Routability Validation in Global Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

ROAD: Routability Analysis and Diagnosis Framework Based on SAT Techniques.
Proceedings of the 2019 International Symposium on Physical Design, 2019

Cuff-Less Blood Pressure Monitoring with a 3-Axis Accelerometer.
Proceedings of the 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2019

2018
Theory and Algorithms of Physical Design.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Tree Structures and Algorithms for Physical Design.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Transient circuit simulation for differential algebraic systems using matrix exponential.
Proceedings of the International Conference on Computer-Aided Design, 2018

Fast and precise routability analysis with conditional design rules.
Proceedings of the 20th System Level Interconnect Prediction Workshop, 2018

Adaptive sensitivity analysis with nonlinear power load modeling.
Proceedings of the 20th System Level Interconnect Prediction Workshop, 2018

2017
Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Exploring the exponential integrators with Krylov subspace algorithms for nonlinear circuit simulation.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
Simulation Algorithms With Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

An Efficient Transient Electro-Thermal Simulation Framework for Power Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A fast time-domain EM-TCAD coupled simulation framework via matrix exponential with stiffness reduction.
Int. J. Circuit Theory Appl., 2016

ePlace-3D: Electrostatics based Placement for 3D-ICs.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

3D floorplan representations: Corner links and partial order.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method.
ACM Trans. Design Autom. Electr. Syst., 2015

ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Simulation Algorithms with Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks.
CoRR, 2015

Power line communication for hybrid power/signal pin SOC design.
Proceedings of the 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, 2015

Developing an online steady-state visual evoked potential-based brain-computer interface system using EarEEG.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

An algorithmic framework for efficient large-scale circuit simulation using exponential integrators.
Proceedings of the 52nd Annual Design Automation Conference, 2015

An interdigitated non-contact ECG electrode for impedance compensation and signal restoration.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014
Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Worst Case Noise Prediction With Nonzero Current Transition Times for Power Grid Planning.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Worst-case noise area prediciton of on-chip power distribution network.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014

MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

ePlace: Electrostatics Based Placement Using Nesterov's Method.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Modeling and Analysis of Power Distribution Networks in 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Worst-case noise prediction using power network impedance profile.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013

Developing stimulus presentation on mobile devices for a truly portable SSVEP-based BCI.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

Empirical mode decomposition improves detection of SSVEP.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

Layer minimization in escape routing for staggered-pin-array PCBs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Power grid simulation using matrix exponential method with rational Krylov subspaces.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

FFTPL: An analytic placement algorithm using fast fourier transform for density equalization.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive Control.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Corrigendum to "A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

An on-chip global broadcast network design with equalized transmission lines in the 1024-core era.
Proceedings of the International Workshop on System Level Interconnect Prediction, 2012

Globally stable, highly parallelizable fast transient circuit simulation via faber series.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph.
Proceedings of the International Symposium on Physical Design, 2012

Circuit simulation via matrix exponential method for stiffness handling and parallel processing.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

A fast time-domain EM-TCAD coupled simulation framework via matrix exponential.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Measuring Steady-State Visual Evoked Potentials from non-hair-bearing areas.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

Character design and stamp algorithms for Character Projection Electron-Beam Lithography.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Prediction and Comparison of High-Performance On-Chip Global Interconnection.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

More realistic power grid verification based on hierarchical current and power constraints.
Proceedings of the 2011 International Symposium on Physical Design, 2011

Placement and beyond in honor of Ernest S. Kuh.
Proceedings of the 2011 International Symposium on Physical Design, 2011

A fast and stable explicit integration method by matrix exponential operator for large scale circuit simulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A block-diagonal structured model reduction scheme for power grid networks.
Proceedings of the Design, Automation and Test in Europe, 2011

Circuit simulation using matrix exponential method.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Exploring 3D power distribution network physics.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Power grid sizing via convex programming.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Linear Dropout Regulator based power distribution design under worst loading.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness.
ACM Trans. Design Autom. Electr. Syst., 2010

Efficient Power Network Analysis with Modeling of Inductive Effects.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Performance prediction of throughput-centric pipelined global interconnects with voltage scaling.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Worst-case performance prediction under supply voltage and temperature variation.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Worst-case noise prediction with non-zero current transition times for early power distribution system verification.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Physical synthesis of bus matrix for high bandwidth low power on-chip communications.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Bus via reduction based on floorplan revising.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

On-chip power network optimization with decoupling capacitors and controlled-ESRs.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

An adaptive parallel flow for power distribution network simulation using discrete Fourier transform.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Enabling power distribution network analysis flows for 3D ICs.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
Energy and switch area optimizations for FPGA global routing architectures.
ACM Trans. Design Autom. Electr. Syst., 2009

Enhancing Learning Effectiveness in Digital Design Courses Through the Use of Programmable Logic Boards.
IEEE Trans. Educ., 2009

Efficient Power Network Analysis Considering Multidomain Clock Gating.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Accurate Eye Diagram Prediction Based on Step Response and Its Application to Low-Power Equalizer Design.
IEICE Trans. Electron., 2009

Predicting the worst-case voltage violation in a 3D power network.
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

Prediction of high-performance on-chip global interconnection.
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

On the bound of time-domain power supply noise based on frequency-domain target impedance.
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

Design methodology of high performance on-chip global interconnect using terminated transmission-line.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Efficient power network analysis with complete inductive modeling.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations.
Proceedings of the 27th International Conference on Computer Design, 2009

3D stacked power distribution considering substrate coupling.
Proceedings of the 27th International Conference on Computer Design, 2009

On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Octilinear redistributive routing in bump arrays.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Parallel transistor level full-chip circuit simulation.
Proceedings of the Design, Automation and Test in Europe, 2009

Reliability aware through silicon via planning for 3D stacked ICs.
Proceedings of the Design, Automation and Test in Europe, 2009

Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.
Proceedings of the 46th Design Automation Conference, 2009

Noise minimization during power-up stage for a multi-domain power network.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

High performance on-chip differential signaling using passive compensation for global communication.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Parallel transistor level circuit simulation using domain decomposition methods.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Design Space Exploration for Power-Efficient Mixed-Radix Ling Adders.
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

2008
Analyzing High-Density ECG Signals Using ICA.
IEEE Trans. Biomed. Eng., 2008

Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Clock Skew Analysis via Vector Fitting in Frequency Domain.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

3-D floorplanning using labeled tree and dual sequences.
Proceedings of the 2008 International Symposium on Physical Design, 2008

On-chip high performance signaling using passive compensation.
Proceedings of the 26th International Conference on Computer Design, 2008

Advancing supercomputer performance through interconnection topology synthesis.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Efficient and accurate eye diagram prediction for high speed signaling.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A novel fixed-outline floorplanner with zero deadspace for hierarchical design.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Low Power Passive Equalizer Design for Computer Memory Links.
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008

Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network.
Proceedings of the Design, Automation and Test in Europe, 2008

Low power passive equalizer optimization using tritonic step response.
Proceedings of the 45th Design Automation Conference, 2008

Timing-power optimization for mixed-radix Ling adders by integer linear programming.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

High performance current-mode differential logic.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Two-Stage Newton-Raphson Method for Transistor-Level Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Efficient Timing Analysis With Known False Paths Using Biclique Covering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Incremental Power Impedance Optimization Using Vector Fitting Modeling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Fast Transient Simulation of Lossy Transmission Lines.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Fast power network analysis with multiple clock domains.
Proceedings of the 25th International Conference on Computer Design, 2007

Passive compensation for high performance inter-chip communication.
Proceedings of the 25th International Conference on Computer Design, 2007

FPGA global routing architecture optimization using a multicommodity flow approach.
Proceedings of the 25th International Conference on Computer Design, 2007

Exploring Cardioneural Signals from Noninvasive ECG Measurement.
Proceedings of the 7th IEEE International Conference on Bioinformatics and Bioengineering, 2007

An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Approaching Speed-of-light Distortionless Communication for On-chip Interconnect.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
On the construction of zero-deficiency parallel prefix circuits with minimum depth.
ACM Trans. Design Autom. Electr. Syst., 2006

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

VLSI Block Placement With Alignment Constraints.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

General Floorplans with L/T-Shaped Blocks Using Corner Block List.
J. Comput. Sci. Technol., 2006

Integrating dynamic thermal via planning with 3D floorplanning algorithm.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Timing model reduction for hierarchical timing analysis.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Layer minimization of escape routing in area array packaging.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

An iterative division algorithm for FPGAs.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

Efficient escape routing for hexagonal array of high density I/Os.
Proceedings of the 43rd Design Automation Conference, 2006

Communication latency aware low power NoC synthesis.
Proceedings of the 43rd Design Automation Conference, 2006

Noninvasive Study of the Human Heart using Independent Component Analysis.
Proceedings of the Sixth IEEE International Symposium on BioInformatics and BioEngineering (BIBE 2006), 2006

An unconditional stable general operator splitting method for transistor level transient analysis.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Efficient static timing analysis using a unified framework for false paths and multi-cycle paths.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Buffer planning as an Integral part of floorplanning with consideration of routing congestion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

The Y architecture for on-chip interconnect: analysis and methodology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Buffer Planning Algorithm Based on Partial Clustered Floorplanning.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Unified quadratic programming approach for mixed mode placement.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Performance constrained floorplanning based on partial clustering [IC layout].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

VLSI block placement with alignment constraints based on corner block list.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Improving the efficiency of static timing analysis with false paths.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Efficient transient simulation for transistor-level analysis.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Constructing zero-deficiency parallel prefix adder of minimum depth.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Integrated algorithmic logical and physical design of integer multiplier.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A multi-level transmission line network approach for multi-giga hertz clock distribution.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Floorplan Representation in VLSI.
Proceedings of the Handbook of Data Structures and Applications., 2004

Stairway compaction using corner block list and its applications with rectilinear blocks.
ACM Trans. Design Autom. Electr. Syst., 2004

Corner block list representation and its application to floorplan optimization.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

Area minimization of power distribution network using efficient nonlinear programming techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

UTACO: a unified timing and congestion optimization algorithm for standard cell global routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Fast postplacement optimization using functional symmetries.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Fast Evaluation of Bounded Slice-Line Grid.
J. Comput. Sci. Technol., 2004

Corner block list representation and its application with boundary constraints.
Sci. China Ser. F Inf. Sci., 2004

A buffer planning algorithm for chip-level floorplanning.
Sci. China Ser. F Inf. Sci., 2004

Fast adders in modern FPGAs.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

A multiple level network approach for clock skew minimization with process variations.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Buffer allocation algorithm with consideration of routing congestion.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A buffer planning algorithm with congestion optimization.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Optimal planning for mesh-based power distribution.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Floorplan representations: Complexity and connections.
ACM Trans. Design Autom. Electr. Syst., 2003

A hierarchical three-way interconnect architecture for hexagonal processors.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

An integrated floorplanning with an efficient buffer planning algorithm.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Arbitrary convex and concave rectilinear block packing based on corner block list.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Evaluating a bounded slice-line grid assignment in O(nlogn) time.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An Algorithmic Approach for Generic Parallel Adders.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Power network analysis using an adaptive algebraic multigrid approach.
Proceedings of the 40th Design Automation Conference, 2003

Realizable parasitic reduction using generalized Y-Delta transformation.
Proceedings of the 40th Design Automation Conference, 2003

Dynamic global buffer planning optimization based on detail block locating and congestion analysis.
Proceedings of the 40th Design Automation Conference, 2003

An algebraic multigrid solver for analytical placement with layout based clustering.
Proceedings of the 40th Design Automation Conference, 2003

RCLK-VJ network reduction with Hurwitz polynomial approximation.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

The Y-architecture: yet another on-chip interconnect solution.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

A buffer planning algorithm based on dead space redistribution.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Toward better wireload models in the presence of obstacles.
IEEE Trans. Very Large Scale Integr. Syst., 2002

An Optimum Placement Search Algorithm Based on Extended Corner Block List.
J. Comput. Sci. Technol., 2002

Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction.
Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002

Balancing the Interconnect Topology for Arrays of Processors between Cost and Power.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Physical Planning Of On-Chip Interconnect Architectures.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001
Floorplanning using a tree representation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Floorplanning with abutment constraints based on corner block list.
Integr., 2001

Interconnect implications of growth-based structural models for VLSI circuits.
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

ECBL: an extended corner block list with solution space including optimum placement.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Revisiting floorplan representations.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Rectilinear block packing using O-tree representation.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List.
Proceedings of the 38th Design Automation Conference, 2001

VLSI floorplanning with boundary constraints based on corner block list.
Proceedings of ASP-DAC 2001, 2001

2000
Tutorial on VLSI Partitioning.
VLSI Design, 2000

An enhanced perturbing algorithm for floorplan design using the O-tree representation.
Proceedings of the 2000 International Symposium on Physical Design, 2000

Hurwitz Stable Reduced Order Modelling for RLC Interconnect Trees.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Block placement with symmetry constraints based on the O-tree non-slicing representation.
Proceedings of the 37th Conference on Design Automation, 2000

Fast post-placement rewiring using easily detectable functional symmetries.
Proceedings of the 37th Conference on Design Automation, 2000

A new efficient waveform simulation method for RLC interconnect via amplitude and phase approximation.
Proceedings of ASP-DAC 2000, 2000

1999
Empirical Study of Block Placement by Cluster Refinement.
VLSI Design, 1999

Sequence-pair approach for rectilinear module placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Timing optimization for multisource nets: characterization andoptimal repeater insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

RLC interconnect delay estimation via moments of amplitude and phase response.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

An O-Tree Representation of Non-Slicing Floorplan and Its Applications.
Proceedings of the 36th Conference on Design Automation, 1999

A Performance-Driven I/O Pin Routing Algorithm.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
Routability improvement using dynamic interconnect architecture.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Rectilinear block placement using sequence-pair.
Proceedings of the 1998 International Symposium on Physical Design, 1998

Extending Moment Computation to 2-Port Circuit Representations.
Proceedings of the 35th Conference on Design Automation, 1998

1997
TIGER: an efficient timing-driven global router for gate array and standard cell layout design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Cluster Refinement for Block Placement.
Proceedings of the 34st Conference on Design Automation, 1997

Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion.
Proceedings of the 34st Conference on Design Automation, 1997

A Network Flow Approach for Hierarchical Tree Partitioning.
Proceedings of the 34st Conference on Design Automation, 1997

A new layout-driven timing model for incremental layout optimization.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

A building block placement tool.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Performance driven bus buffer insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

A wire length estimation technique utilizing neighborhood density equations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Solving the net matching problem in high-performance chip design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

A global router with a theoretical bound on the optimal solution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Simultaneous Routing and Buffer Insertion for High Performance Interconnect.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming.
Proceedings of the 33st Conference on Design Automation, 1996

New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing.
Proceedings of the 33st Conference on Design Automation, 1996

New Spectral Linear Placement and Clustering Approach.
Proceedings of the 33st Conference on Design Automation, 1996

Network Partitioning into Tree Hierarchies.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Physical models and algorithms for optoelectronic MCM layout.
IEEE Trans. Very Large Scale Integr. Syst., 1995

On general zero-skew clock net construction.
IEEE Trans. Very Large Scale Integr. Syst., 1995

Circuit clustering using a stochastic flow injection method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Optimization by iterative improvement: an experimental evaluation on two-way partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

A cell-based hierarchical pitchmatching compaction using minimal LP.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

A replication cut for two-way partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Local ratio cut and set covering partitioning for huge logic emulation systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Optimization of power dissipation and skew sensitivity in clock buffer synthesis.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Finite State Machine Decomposition for I/O Minimization.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Simple tree-construction heuristics for the fanout problem .
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

A gradient method on the initial partition of Fiduccia-Mattheyses algorithm.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Optimal wire sizing and buffer insertion for low power and a generalized delay model.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Linear decomposition algorithm for VLSI design applications.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Performance-Driven Partitioning Using a Replication Graph Approach.
Proceedings of the 32st Conference on Design Automation, 1995

Performance driven multiple-source bus synthesis using buffer insertion.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Block-oriented programmable design with switching network interconnect.
IEEE Trans. Very Large Scale Integr. Syst., 1994

A general purpose, multiple-way partitioning algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

A multi-probe approach for MCM substrate testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Skew sensitivity minimization of buffered clock tree.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Data Flow Partitioning for Clock Period and Latency Minimization.
Proceedings of the 31st Conference on Design Automation, 1994

Circuit Partitioning for Huge Logic Emulation Systems.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Performance-driven partitioning using retiming and replication.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

An efficient algorithm for the net matching problem.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

An Efficient Timing-Driven Global Routing Algorithm.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Performance-Driven Steiner Tree Algorithm for Global Routing.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

<i>Prime</i>: A Timing-Driven Placement Tool using A Piecewise Linear Resistive Network Approach.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Geometric compaction on channel routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Symbolic layout compaction under conditional design rules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

The optimal partitioning of networks.
Networks, 1992

Maximum Concurrent Flows and Minimum Cuts.
Algorithmica, 1992

A probabilistic multicommodity-flow solution to circuit clustering problems.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

An optimal probe testing algorithm for the connectivity verification of MCM substrates.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

FARM: An Efficient Feed-Through Pin Assignment Algorithm.
Proceedings of the 29th Design Automation Conference, 1992

1991
Ratio cut partitioning for hierarchical designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

An improved two-way partitioning algorithm with stable performance [VLSI].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

The Orientation of Modules Based on Graph Decomposition.
IEEE Trans. Computers, 1991

Ancestor tree for arbitrary multi-terminal cut functions.
Ann. Oper. Res., 1991

A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow Algorithm.
Proceedings of the 28th Design Automation Conference, 1991

1990
A Two-Level Two-Way Partitioning Algorithm.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989
Towards efficient hierarchical designs by ratio cut partitioning.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
Improved Channel Routing by Via Minimization and Shifting.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
Linear placement algorithms and applications to VLSI design.
Networks, 1987

1984
Module Placement Based on Resistive Network Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984


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