Etienne Bergeron

According to our database, Etienne Bergeron authored at least 5 papers between 2004 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2011

Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation.

Etienne Bergeron, Louis-David Perron, Marc Feeley, Jean-Pierre David

ACM Trans. Reconfigurable Technol. Syst., 2011

2008

Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs.

Etienne Bergeron, Marc Feeley, Jean-Pierre David

Proceedings of the Compiler Construction, 17th International Conference, 2008

2005

High Level Synthesis for Data-Driven Applications.

Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley, Jean-Pierre David

Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

2004

A Step towards Intelligent Translation from High-Level Design to RTL.

Jean-Pierre David, Etienne Bergeron

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

An Intermediate Level HDL for System Level Design.

Jean-Pierre David, Etienne Bergeron

Proceedings of the Forum on specification and Design Languages, 2004