Jean-Pierre David

According to our database1, Jean-Pierre David authored at least 44 papers between 1996 and 2018.

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Bibliography

2018
An Evaluation of a High-Level Synthesis Approach to the FPGA-Based Submicrosecond Real-Time Simulation of Power Converters.
IEEE Trans. Industrial Electronics, 2018

Ultra-low latency communication channels for FPGA-based HPC cluster.
Integration, 2018

2017
Low latency and division free Gauss-Jordan solver in floating point arithmetic.
J. Parallel Distrib. Comput., 2017

A data driven CGRA Overlay Architecture with embedded processors.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A Cache-Coherent Heterogeneous Architecture for Low Latency Real Time Applications.
Proceedings of the 20th IEEE International Symposium on Real-Time Distributed Computing, 2017

2015
BinaryConnect: Training Deep Neural Networks with binary weights during propagations.
CoRR, 2015

Low latency solver for linear equation systems in floating point arithmetic.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

BinaryConnect: Training Deep Neural Networks with binary weights during propagations.
Proceedings of the Advances in Neural Information Processing Systems 28: Annual Conference on Neural Information Processing Systems 2015, 2015

Intermediate-Level Synthesis of a Gauss-Jordan Elimination Linear Solver.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Mapping applications on two-level configurable hardware.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014
Low precision arithmetic for deep learning.
CoRR, 2014

Fast description and synthesis of control-dominant circuits.
Computers & Electrical Engineering, 2014

2013
Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators.
TRETS, 2013

A fully automated reconfigurable calculation engine dedicated to the real-time simulation of high switching frequency power electronic circuits.
Mathematics and Computers in Simulation, 2013

Max-hashing fragments for large data sets detection.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

High-Level Description and Synthesis of Floating-Point Accumulators on FPGA.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012
A State-Space Modeling Approach for the FPGA-Based Real-Time Simulation of High Switching Frequency Power Converters.
IEEE Trans. Industrial Electronics, 2012

Synchronized-transfer-level design methodology applied to hardware matrix multiplication.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Effective floating-point calculation engines intended for the FPGA-based HIL simulation.
Proceedings of the 21st IEEE International Symposium on Industrial Electronics, 2012

Two-level configuration for FPGA: A new design methodology based on a computing fabric.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Raising the abstraction level of HDL for control-dominant applications.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation.
TRETS, 2011

A High-Resolution Time-to-Digital Converter on FPGA Using Dynamic Reconfiguration.
IEEE Trans. Instrumentation and Measurement, 2011

2010
Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Performing Floating-Point Accumulation on a Modern FPGA in Single and Double Precision.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

2009
A Scalable Architecture for Multivariate Polynomial Evaluation on FPGA.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

2008
Application Specific Instruction set processor specialized for block motion estimation.
Proceedings of the 26th International Conference on Computer Design, 2008

Setting up On-Line Learning Experiments: The LearningLab Platform.
Proceedings of the 8th IEEE International Conference on Advanced Learning Technologies, 2008

Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs.
Proceedings of the Compiler Construction, 17th International Conference, 2008

2007
Hardware Complexity of Modular Multiplication and Exponentiation.
IEEE Trans. Computers, 2007

2006
Expressing Learning Scenarios with Computer Independent Models.
Proceedings of the 6th IEEE International Conference on Advanced Learning Technologies, 2006

Comparing Educational Modeling Languages on a Case Study.
Proceedings of the 6th IEEE International Conference on Advanced Learning Technologies, 2006

LDL: An Alternative EML.
Proceedings of the 6th IEEE International Conference on Advanced Learning Technologies, 2006

Modeling Collaborative Learning Activities on e-Learning Platforms.
Proceedings of the 6th IEEE International Conference on Advanced Learning Technologies, 2006

Expressing Workshop Scenario with Computer Independent Model.
Proceedings of the 6th IEEE International Conference on Advanced Learning Technologies, 2006

2005
High Level Synthesis for Data-Driven Applications.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

2004
A Step towards Intelligent Translation from High-Level Design to RTL.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

An Intermediate Level HDL for System Level Design.
Proceedings of the Forum on specification and Design Languages, 2004

2002
A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation.
Proceedings of the Field-Programmable Logic and Applications, 2002

An FPGA Implementation of the Linear Cryptanalysis.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
Implementation of very large dataflow graphs on a reconfigurable architecture for robotic applications.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

1998
A Data-Flow Oriented Co-Design for Reconfigurable Systems.
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

1996
Hypermedia Exercises Prototyping and Modelising.
Proceedings of the Computer Aided Learning and Instruction in Science and Engineering, 1996


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