Fahimeh Jafari

Clust. Comput., October, 2025

RadarSeq: A Temporal Vision Framework for User Churn Prediction via Radar Chart Sequences.

[BibT_eX]

[DOI]

Sina Najafi

M. Hadi Sepanj

CoRR, June, 2025

2021

Designing a Cost-Efficient Network for a Small Enterprise.

[BibT_eX]

[DOI]

Lucky Osemwengie

Amin Karami

Proceedings of the Intelligent Computing, 2021

2017

A Customized Design of Smart Home using Internet-of-Things.

[BibT_eX]

[DOI]

Mukendi Nathan Kadima

Proceedings of the 9th International Conference on Information Management and Engineering, Barcelona, Spain, October 09, 2017

A Secure Smart Home using Internet-of-Things.

[BibT_eX]

[DOI]

Jabir Muhammad Ibrahim

Amin Karami

Proceedings of the 9th International Conference on Information Management and Engineering, Barcelona, Spain, October 09, 2017

2016

Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

2015

Analysis and Management of Communication in On-Chip Networks.

[BibT_eX]

[DOI]

PhD thesis, 2015

Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

2012

Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Optimal Selection of Function Implementation in a Hierarchical Configware Synthesis Method for a Coarse Grain Reconfigurable Architecture.

[BibT_eX]

[DOI]

Shuo Li

Ahmed Hemani

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

Buffer Optimization in Network-on-Chip Through Flow Regulation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Proportionally fair flow control mechanism for best effort traffic in network-on-chip architectures.

[BibT_eX]

[DOI]

Int. J. Parallel Emergent Distributed Syst., 2010

Optimal regulation of traffic flows in networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Throughput-fairness tradeoff in Best Effort flow control for on-chip architectures.

[BibT_eX]

[DOI]

Mohamed Ould-Khaoua

Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

2008

A Novel Congestion Control Scheme in Network-on-Chip Based on Best Effort Delay-Sum Optimization.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Parallel Architectures, 2008

Proportionally-fair best effort flow control in network-on-chip architectures.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Max-Min-Fair Best Effort Flow Control in Network-on-Chip Architectures.

[BibT_eX]

[DOI]

Proceedings of the Computational Science, 2008

Best Effort Flow Control in Network-on-Chip.

[BibT_eX]

[DOI]

Mohammad Hossein Yaghmaee

Proceedings of the Advances in Computer Science and Engineering, 2008

2007

A Novel Flow Control Scheme for Best Effort Traffic in NoC Based on Source Rate Utility Maximization.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on Modeling, 2007

A Novel Congestion Control Scheme for Elastic Flows in Network-on-Chip Based on Sum-Rate Optimization.

[BibT_eX]

[DOI]