Fahimeh Jafari

Orcid: 0000-0003-3847-3092

According to our database1, Fahimeh Jafari authored at least 19 papers between 2007 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Designing a Cost-Efficient Network for a Small Enterprise.
Proceedings of the Intelligent Computing, 2021

2017
A Customized Design of Smart Home using Internet-of-Things.
Proceedings of the 9th International Conference on Information Management and Engineering, Barcelona, Spain, October 09, 2017

A Secure Smart Home using Internet-of-Things.
Proceedings of the 9th International Conference on Information Management and Engineering, Barcelona, Spain, October 09, 2017

2016
Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
Analysis and Management of Communication in On-Chip Networks.
PhD thesis, 2015

Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels.
ACM Trans. Design Autom. Electr. Syst., 2015

2012
Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Optimal Selection of Function Implementation in a Hierarchical Configware Synthesis Method for a Coarse Grain Reconfigurable Architecture.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Buffer Optimization in Network-on-Chip Through Flow Regulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Proportionally fair flow control mechanism for best effort traffic in network-on-chip architectures.
Int. J. Parallel Emergent Distributed Syst., 2010

Optimal regulation of traffic flows in networks-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Throughput-fairness tradeoff in Best Effort flow control for on-chip architectures.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

2008
A Novel Congestion Control Scheme in Network-on-Chip Based on Best Effort Delay-Sum Optimization.
Proceedings of the 9th International Symposium on Parallel Architectures, 2008

Proportionally-fair best effort flow control in network-on-chip architectures.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Max-Min-Fair Best Effort Flow Control in Network-on-Chip Architectures.
Proceedings of the Computational Science, 2008

Best Effort Flow Control in Network-on-Chip.
Proceedings of the Advances in Computer Science and Engineering, 2008

2007
A Novel Flow Control Scheme for Best Effort Traffic in NoC Based on Source Rate Utility Maximization.
Proceedings of the 15th International Symposium on Modeling, 2007

A Novel Congestion Control Scheme for Elastic Flows in Network-on-Chip Based on Sum-Rate Optimization.
Proceedings of the Computational Science and Its Applications, 2007


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