Zhonghai Lu

Proceedings of the Model-Based Safety and Assessment - 5th International Symposium, 2017

A Methodological Framework for Model-Based Self-management of Services and Components in Dependable Cyber-Physical Systems.

[BibT_eX]

[DOI]

De-Jiu Chen

Proceedings of the Advances in Dependability Engineering of Complex Systems, 2017

Lifetime adaptive ECC in NAND flash page management.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Prediction based convolution neural network acceleration: work-in-progress.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Compilers, 2017

SSS: self-aware system-on-chip using static-dynamic hybrid method (work-in-progress).

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Compilers, 2017

2016

A New CDMA Encoding/Decoding Method for on-Chip Communication Network.

[BibT_eX]

[DOI]

Jian Wang

Yubai Li

IEEE Trans. Very Large Scale Integr. Syst., 2016

Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

A 101.4 GOPS/W Reconfigurable and Scalable Control-Centric Embedded Processor for Domain-Specific Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Aggregate Flow-Based Performance Fairness in CMPs.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2016

Design and implementation of multi-mode routers for large-scale inter-core networks.

[BibT_eX]

[DOI]

Integr., 2016

Service-Guaranteed Multi-port Packet Memory for Parallel Protocol Processing Architecture.

[BibT_eX]

[DOI]

Mohammad Badawi

Ahmed Hemani

Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Multi-bit transient fault control for NoC links using 2D fault coding method.

[BibT_eX]

[DOI]

Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

A 101.4 GOPS/W reconfigurable and scalable control-centric embedded processor for domain-specific applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Opportunistic Competition Overhead Reduction for Expediting Critical Section in NoC Based CMPs.

[BibT_eX]

[DOI]

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

DVFS for NoCs in CMPs: A thread voting approach.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Real-Time Analysis for Wormhole NoC: Revisited and Revised.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Elastic Management and QoS Provisioning Scheme for Adaptable Multi-core Protocol Processing Architecture.

[BibT_eX]

[DOI]

Mohammad Badawi

Ahmed Hemani

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Memory-access aware DVFS for network-on-chip in CMPs.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

OLITS: An Ohm's Law-like traffic splitting model based on congestion prediction.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

Heuristics-Aided Tightness Evaluation of Analytical Bounds in Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips.

[BibT_eX]

[DOI]

J. Softw., 2015

MultiCS: Circuit switched NoC with multiple sub-networks and sub-channels.

[BibT_eX]

[DOI]

J. Syst. Archit., 2015

Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2015

Implementing MVC Decoding on Homogeneous NoCs: Circuit Switching or Wormhole Switching.

[BibT_eX]

[DOI]

Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Highway in TDM NoCs.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Backlog Bound Analysis for Virtual-Channel Routers.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Validating Delay Bounds in Networks on Chip: Tightness and Pitfalls.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Exploring stacked main memory architecture for 3D GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Performance analysis of on-chip bufferless router with multi-ejection ports.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

A Fair and Maximal Allocator for Single-Cycle On-Chip Homogeneous Resource Allocation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Item-Level Indoor Localization With Passive UHF RFID Based on Tag Interaction Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Electron., 2014

A survey of memory architecture for 3D chip multi-processors.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

A hierarchical reconfigurable micro-coded multi-core processor for IoT applications.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Towards stochastic delay bound analysis for Network-on-Chip.

[BibT_eX]

[DOI]

Yuming Jiang

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

An analytical model for worst-case reorder buffer size of multi-path minimal routing NoCs.

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Empowering study of delay bound tightness with simulated annealing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Analysis and evaluation of per-flow delay bound for multiplexing models.

[BibT_eX]

[DOI]

Yanchen Long

Xiaolang Yan

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Parallel probe based dynamic connection setup in TDM NoCs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Fuzzy flow regulation for Network-on-Chip based chip multiprocessors systems.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Customizable coarse-grained energy-efficient reconfigurable packet processing architecture.

[BibT_eX]

[DOI]

Mohammad Badawi

Ahmed Hemani

Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013

An Analytical Latency Model for Networks-on-Chip.

[BibT_eX]

[DOI]

Abbas Eslami Kiasari

IEEE Trans. Very Large Scale Integr. Syst., 2013

Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Scalability Analysis of Memory Consistency Models in NoC-Based Distributed Shared Memory SoCs.

[BibT_eX]

[DOI]

Abdul Naeem

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Mathematical formalisms for performance evaluation of networks-on-chip.

[BibT_eX]

[DOI]

Abbas Eslami Kiasari

ACM Comput. Surv., 2013

Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2013

Per-flow delay bound analysis based on a formalized microarchitectural model.

[BibT_eX]

[DOI]

Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Efficient distributed memory management in a multi-core H.264 decoder on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on System on Chip, 2013

Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

Three-phase time-aware energy minimization with DVFS and unrolling for Chip Multiprocessors.

[BibT_eX]

[DOI]

J. Syst. Archit., 2012

TPSS: A Flexible Hardware Support for Unicast and Multicast on Network-on-Chip.

[BibT_eX]

[DOI]

J. Comput., 2012

A Survey of FPGA Dynamic Reconfiguration Design Methodology and Applications.

[BibT_eX]

[DOI]

Int. J. Embed. Real Time Commun. Syst., 2012

Performance Analysis of Flow-Based Traffic Splitting Strategy on Cluster-Mesh Sensor Networks.

[BibT_eX]

[DOI]

Int. J. Distributed Sens. Networks, 2012

Code division multiple access/pulse position modulation ultra-wideband radio frequency identification for Internet of Things: concept and analysis.

[BibT_eX]

[DOI]

Int. J. Commun. Syst., 2012

Design and Optimization of a CDMA-Based Multi-Reader Passive UHF RFID System for Dense Scenarios.

[BibT_eX]

[DOI]

IEICE Trans. Commun., 2012

Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2012

A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2012

Self-selection pseudo- circuit: a clever crossbar pre-allocation.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2012

A single-cycle output buffered router with layered switching for Networks-on-Chips.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2012

An Enhanced IOT Gateway in a Broadcast System.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Ubiquitous Intelligence and Computing and 9th International Conference on Autonomic and Trusted Computing, 2012

Modeling and Power Evaluation of On-Chip Router Components in Spintronics.

[BibT_eX]

[DOI]

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Dynamic Flow Regulation for IP Integration on Network-on-Chip.

[BibT_eX]

[DOI]

Yi Wang

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

System-level evaluation of sensor networks deployment strategies: Coverage, lifetime and cost.

[BibT_eX]

[DOI]

Huimin She

Proceedings of the 8th International Wireless Communications and Mobile Computing Conference, 2012

Scalability analysis of release and sequential consistency models in NoC based multicore systems.

[BibT_eX]

[DOI]

Abdul Naeem

Proceedings of the 2012 International Symposium on System on Chip, 2012

Architecture Support and Comparison of Three Memory Consistency Models in NoC Based Systems.

[BibT_eX]

[DOI]

Abdul Naeem

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routing.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Analytical approaches for performance evaluation of networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Compilers, 2012

2011

System design of full HD MVC decoding on mesh-based multicore NoCs.

[BibT_eX]

[DOI]

Ning Ma

Li-Rong Zheng

Microprocess. Microsystems, 2011

Hybrid Distributed Shared Memory Space in Multi-core Processors.

[BibT_eX]

[DOI]

J. Softw., 2011

Cooperative communication based barrier synchronization in on-chip mesh architectures.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2011

Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations.

[BibT_eX]

[DOI]

Iraklis Anagnostopoulos

IEEE Embed. Syst. Lett., 2011

FPGA-Based Particle Recognition in the HADES Experiment.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2011

A High-End Reconfigurable Computation Platform for Nuclear and Particle Physics Experiments.

[BibT_eX]

[DOI]

Comput. Sci. Eng., 2011

Modeling and analysis of Rayleigh fading channels using stochastic network calculus.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE Wireless Communications and Networking Conference, 2011

Network-on-Chip multicasting with low latency path setup.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Stochastic coverage in event-driven sensor networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE 22nd International Symposium on Personal, 2011

Cross clock-domain TDM virtual circuits for networks on chips.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2011, 2011

A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems.

[BibT_eX]

[DOI]

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Jamming-resilient multi-radio multi-channel multihop wireless network for smart grid.

[BibT_eX]

[DOI]

Proceedings of the 7th Cyber Security and Information Intelligence Research Workshop, 2011

Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Power-efficient tree-based multicast support for Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Evaluation of deflection routing on various NoC topologies.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

FPGA-Based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010

Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Buffer Optimization in Network-on-Chip Through Flow Regulation.

[BibT_eX]

[DOI]

Mohammad Hossien Yaghmaee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

System-level exploration of mesh-based NoC architectures for multimedia applications.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Reducing FPGA Reconfiguration Time Overhead using Virtual Configurations.

[BibT_eX]

Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010

Run-Time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips.

[BibT_eX]

[DOI]

Proceedings of the Third International Symposium on Parallel Architectures, 2010

A framework for designing congestion-aware deterministic routing.

[BibT_eX]

[DOI]

Abbas Eslami Kiasari

Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

Inter-process Communication Using Pipes in FPGA-Based Adaptive Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

The MOSART Mapping Optimization for Multi-Core ARchiTectures.

[BibT_eX]

[DOI]

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Scalability of weak consistency in NoC based multicore architectures.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

QoS scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin.

[BibT_eX]

[DOI]

Qiang Dou

Proceedings of the 28th International Conference on Computer Design, 2010

A Low Delay Multiple Reader Passive RFID System Using Orthogonal TH-PPM IR-UWB.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Computer Communications and Networks, 2010

COSMO: CO-Simulation with MATLAB and OMNeT++ for Indoor Wireless Networks.

[BibT_eX]

[DOI]

Proceedings of the Global Communications Conference, 2010

FPGA-based adaptive computing for correlated multi-stream processing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Optimal regulation of traffic flows in networks-on-chip.

[BibT_eX]

[DOI]

Mohammad Hossien Yaghmaee

Proceedings of the Design, Automation and Test in Europe, 2010

Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Scalability of relaxed consistency models in NoC based multicore architectures.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2009

Analyzing Credit-Based Router-to-Router Flow Control for On-Chip Networks.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2009

Worst-Case Flit and Packet Delay Bounds in Wormhole Networks on Chip.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the 69th IEEE Vehicular Technology Conference, 2009

A flow regulator for On-Chip Communication.

[BibT_eX]

[DOI]

Dimitris Brachos

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

A Reconfigurable Design Framework for FPGA Adaptive Computing.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Scalability of network-on-chip communication architecture for 3-D meshes.

[BibT_eX]

[DOI]

Awet Yemane Weldezion

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip.

[BibT_eX]

[DOI]

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

From 2D to 3D NoCs: A case study on worst-case communication performance.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Run-time Partial Reconfiguration speed investigation and architectural design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Exploration of Slot Allocation for On-Chip TDM Virtual Circuits.

[BibT_eX]

[DOI]

Li Tong

Hua Zhang

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Flow regulation for on-chip communication.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Applying network calculus for performance analysis of self-similar traffic in on-chip networks.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Analysis of communication delay bounds for network on chips.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

3-D memory organization and performance analysis for multi-processor network-on-chip architecture.

[BibT_eX]

[DOI]

Awet Yemane Weldezion

Roshan Weerasekera

Hannu Tenhunen

Proceedings of the IEEE International Conference on 3D System Integration, 2009

Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh.

[BibT_eX]

[DOI]

Matt Grange

Awet Yemane Weldezion

Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008

TDM Virtual-Circuit Configuration for Network-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

ATCA-based computation platform for data acquisition and triggering in particle physics experiments.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip.

[BibT_eX]

[DOI]

Lei Xia

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Dynamic TDM virtual circuit implementation for NoC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

Design and Analysis of On-Chip Communication for Network-on-Chip Platforms.

[BibT_eX]

[DOI]

PhD thesis, 2007

Admitting and ejecting flits in wormhole-switched networks on chip.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Hardware/Software Co-design of a General-Purpose Computation Platform in Particle Physics.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Traffic Splitting with Network Calculus for Mesh Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the Future Generation Communication and Networking, 2007

Layered Switching for Networks on Chip.

[BibT_eX]

[DOI]

Ming Liu

Proceedings of the 44th Design Automation Conference, 2007

2006

Connection-oriented Multicasting in Wormhole-switched Networks on Chip.

[BibT_eX]

[DOI]

Bei Yin

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Evaluation of on-chip networks using deflection routing.

[BibT_eX]

[DOI]

Mingchen Zhong

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005

Traffic Configuration for Evaluating Networks on Chips.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Refinement of Perfectly Synchronous Communication Model.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2005

Feasibility analysis of messages for on-chip networks using wormhole routing.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Flit admission in on-chip wormhole-switched networks with virtual channels.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on System-on-Chip, 2004

2003

Development and Application of Design Transformations in ForSyDe.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

NoC Application Programming Interfaces.

[BibT_eX]

[DOI]

Raimo Haukilahti

Proceedings of the Networks on Chip, 2003

2002

A Case Study of Hardware and Software Synthesis in ForSyDe.

[BibT_eX]

[DOI]