Zhonghai Lu

According to our database1, Zhonghai Lu authored at least 179 papers between 2002 and 2019.

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Bibliography

2019
Security-Aware Task Mapping Reducing Thermal Side Channel Leakage in CMPs.
IEEE Trans. Industrial Informatics, 2019

Bit-Flipping Schemes Upon MLC Flash: Investigation, Implementation, and Evaluation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

SCORE: A Novel Scheme to Efficiently Cache Overlong ECCs in NAND Flash Memory.
TACO, 2019

SSS: Self-aware System-on-chip Using a Static-dynamic Hybrid Method.
JETC, 2019

Toward FPGA Security in IoT: A New Detection Technique for Hardware Trojans.
IEEE Internet of Things Journal, 2019

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory.
IEEE Access, 2019

Congestion-Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Smilodon: An Efficient Accelerator for Low Bit-Width CNNs with Task Partitioning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Advance Virtual Channel Reservation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Characterizing the Reliability and Threshold Voltage Shifting of 3D Charge Trap NAND Flash.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

ANN Based Admission Control for On-Chip Networks.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition.
IEEE Trans. VLSI Syst., 2018

RoB-Router : A Reorder Buffer Enabled Low Latency Network-on-Chip Router.
IEEE Trans. Parallel Distrib. Syst., 2018

Characterizing 3D Floating Gate NAND Flash: Observations, Analyses, and Implications.
TOS, 2018

A New Parallel CODEC Technique for CDMA NoCs.
IEEE Trans. Industrial Electronics, 2018

WARD: Wear Aware RAID Design Within SSDs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

xMAS-Based QoS Analysis Methodology.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Composable Worst-Case Delay Bound Analysis Using Network Calculus.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Thread Voting DVFS for Manycore NoCs.
IEEE Trans. Computers, 2018

Cache Access Fairness in 3D Mesh-Based NUCA.
IEEE Access, 2018

Exploiting Minipage-Level Mapping to Improve Write Efficiency of NAND Flash.
Proceedings of the 2018 IEEE International Conference on Networking, 2018

Towards QoS-Aware Service-Oriented Communication in E/E Automotive Architectures.
Proceedings of the IECON 2018, 2018

Characterizing 3D Charge Trap NAND Flash: Observations, Analyses and Applications.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

iNPG: Accelerating Critical Section Access with In-network Packet Generation for NoC Based Many-Cores.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

Program error rate-based wear leveling for NAND flash memory.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Dynamic Traffic Regulation in NoC-Based Systems.
IEEE Trans. VLSI Syst., 2017

A Tool for xMAS-Based Modeling and Analysis of Communication Fabrics in Simulink.
ACM Trans. Model. Comput. Simul., 2017

Round-trip DRAM Access Fairness in 3D NoC-based Many-core Systems.
ACM Trans. Embedded Comput. Syst., 2017

Extending Real-Time Analysis for Wormhole NoCs.
IEEE Trans. Computers, 2017

Marginal Performance: Formalizing and Quantifying Power Over/Under Provisioning in NoC DVFS.
IEEE Trans. Computers, 2017

Quality-of-service-aware adaptation scheme for multi-core protocol processing architecture.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

Characterizing 3D Floating Gate NAND Flash.
Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, Urbana-Champaign, IL, USA, June 05, 2017

ALARM: A Location-Aware Redistribution Method to Improve 3D FG NAND Flash Reliability.
Proceedings of the 2017 International Conference on Networking, Architecture, and Storage, 2017

A Model-Based Approach to Dynamic Self-assessment for Automated Performance and Safety Awareness of Cyber-Physical Systems.
Proceedings of the Model-Based Safety and Assessment - 5th International Symposium, 2017

A Methodological Framework for Model-Based Self-management of Services and Components in Dependable Cyber-Physical Systems.
Proceedings of the Advances in Dependability Engineering of Complex Systems, 2017

Lifetime adaptive ECC in NAND flash page management.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Prediction based convolution neural network acceleration: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017

SSS: self-aware system-on-chip using static-dynamic hybrid method (work-in-progress).
Proceedings of the 2017 International Conference on Compilers, 2017

2016
A New CDMA Encoding/Decoding Method for on-Chip Communication Network.
IEEE Trans. VLSI Syst., 2016

Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip.
IEEE Trans. VLSI Syst., 2016

A 101.4 GOPS/W Reconfigurable and Scalable Control-Centric Embedded Processor for Domain-Specific Applications.
IEEE Trans. on Circuits and Systems, 2016

Aggregate Flow-Based Performance Fairness in CMPs.
TACO, 2016

Design and implementation of multi-mode routers for large-scale inter-core networks.
Integration, 2016

Service-Guaranteed Multi-port Packet Memory for Parallel Protocol Processing Architecture.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Multi-bit transient fault control for NoC links using 2D fault coding method.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

A 101.4 GOPS/W reconfigurable and scalable control-centric embedded processor for domain-specific applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Opportunistic Competition Overhead Reduction for Expediting Critical Section in NoC Based CMPs.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

DVFS for NoCs in CMPs: A thread voting approach.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Real-Time Analysis for Wormhole NoC: Revisited and Revised.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Elastic Management and QoS Provisioning Scheme for Adaptable Multi-core Protocol Processing Architecture.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Memory-access aware DVFS for network-on-chip in CMPs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

OLITS: An Ohm's Law-like traffic splitting model based on congestion prediction.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels.
ACM Trans. Design Autom. Electr. Syst., 2015

Heuristics-Aided Tightness Evaluation of Analytical Bounds in Networks-on-Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips.
JSW, 2015

MultiCS: Circuit switched NoC with multiple sub-networks and sub-channels.
Journal of Systems Architecture - Embedded Systems Design, 2015

Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications.
J. Electrical and Computer Engineering, 2015

Implementing MVC Decoding on Homogeneous NoCs: Circuit Switching or Wormhole Switching.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Highway in TDM NoCs.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Backlog Bound Analysis for Virtual-Channel Routers.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Validating Delay Bounds in Networks on Chip: Tightness and Pitfalls.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Exploring stacked main memory architecture for 3D GPGPUs.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Performance analysis of on-chip bufferless router with multi-ejection ports.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
A Fair and Maximal Allocator for Single-Cycle On-Chip Homogeneous Resource Allocation.
IEEE Trans. VLSI Syst., 2014

Item-Level Indoor Localization With Passive UHF RFID Based on Tag Interaction Analysis.
IEEE Trans. Industrial Electronics, 2014

A survey of memory architecture for 3D chip multi-processors.
Microprocessors and Microsystems - Embedded Hardware Design, 2014

Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs.
IEICE Electronic Express, 2014

A hierarchical reconfigurable micro-coded multi-core processor for IoT applications.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Towards stochastic delay bound analysis for Network-on-Chip.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

An analytical model for worst-case reorder buffer size of multi-path minimal routing NoCs.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Empowering study of delay bound tightness with simulated annealing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Analysis and evaluation of per-flow delay bound for multiplexing models.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Parallel probe based dynamic connection setup in TDM NoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Fuzzy flow regulation for Network-on-Chip based chip multiprocessors systems.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Customizable coarse-grained energy-efficient reconfigurable packet processing architecture.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
An Analytical Latency Model for Networks-on-Chip.
IEEE Trans. VLSI Syst., 2013

Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router.
IEEE Trans. VLSI Syst., 2013

Scalability Analysis of Memory Consistency Models in NoC-Based Distributed Shared Memory SoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Code division multiple access/pulse position modulation ultra-wideband radio frequency identification for Internet of Things: concept and analysis.
Int. J. Communication Systems, 2013

Mathematical formalisms for performance evaluation of networks-on-chip.
ACM Comput. Surv., 2013

Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property.
Computers & Electrical Engineering, 2013

Per-flow delay bound analysis based on a formalized microarchitectural model.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Efficient distributed memory management in a multi-core H.264 decoder on FPGA.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Three-phase time-aware energy minimization with DVFS and unrolling for Chip Multiprocessors.
Journal of Systems Architecture - Embedded Systems Design, 2012

TPSS: A Flexible Hardware Support for Unicast and Multicast on Network-on-Chip.
JCP, 2012

A Survey of FPGA Dynamic Reconfiguration Design Methodology and Applications.
IJERTCS, 2012

Performance Analysis of Flow-Based Traffic Splitting Strategy on Cluster-Mesh Sensor Networks.
IJDSN, 2012

Design and Optimization of a CDMA-Based Multi-Reader Passive UHF RFID System for Dense Scenarios.
IEICE Transactions, 2012

Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip.
IEICE Transactions, 2012

A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip.
IEICE Transactions, 2012

Self-selection pseudo- circuit: a clever crossbar pre-allocation.
IEICE Electronic Express, 2012

A single-cycle output buffered router with layered switching for Networks-on-Chips.
Computers & Electrical Engineering, 2012

An Enhanced IOT Gateway in a Broadcast System.
Proceedings of the 9th International Conference on Ubiquitous Intelligence and Computing and 9th International Conference on Autonomic and Trusted Computing, 2012

Modeling and Power Evaluation of On-Chip Router Components in Spintronics.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Dynamic Flow Regulation for IP Integration on Network-on-Chip.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

System-level evaluation of sensor networks deployment strategies: Coverage, lifetime and cost.
Proceedings of the 8th International Wireless Communications and Mobile Computing Conference, 2012

Scalability analysis of release and sequential consistency models in NoC based multicore systems.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Architecture Support and Comparison of Three Memory Consistency Models in NoC Based Systems.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routing.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Analytical approaches for performance evaluation of networks-on-chip.
Proceedings of the 15th International Conference on Compilers, 2012

2011
System design of full HD MVC decoding on mesh-based multicore NoCs.
Microprocessors and Microsystems - Embedded Hardware Design, 2011

Hybrid Distributed Shared Memory Space in Multi-core Processors.
JSW, 2011

Cooperative communication based barrier synchronization in on-chip mesh architectures.
IEICE Electronic Express, 2011

Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations.
Embedded Systems Letters, 2011

FPGA-Based Particle Recognition in the HADES Experiment.
IEEE Design & Test of Computers, 2011

A High-End Reconfigurable Computation Platform for Nuclear and Particle Physics Experiments.
Computing in Science and Engineering, 2011

Modeling and analysis of Rayleigh fading channels using stochastic network calculus.
Proceedings of the 2011 IEEE Wireless Communications and Networking Conference, 2011

Network-on-Chip multicasting with low latency path setup.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Stochastic coverage in event-driven sensor networks.
Proceedings of the IEEE 22nd International Symposium on Personal, 2011

Cross clock-domain TDM virtual circuits for networks on chips.
Proceedings of the NOCS 2011, 2011

A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Jamming-resilient multi-radio multi-channel multihop wireless network for smart grid.
Proceedings of the 7th Cyber Security and Information Intelligence Research Workshop, 2011

Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Power-efficient tree-based multicast support for Networks-on-Chip.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Evaluation of deflection routing on various NoC topologies.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

FPGA-Based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Buffer Optimization in Network-on-Chip Through Flow Regulation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

System-level exploration of mesh-based NoC architectures for multimedia applications.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Run-Time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips.
Proceedings of the Third International Symposium on Parallel Architectures, 2010

A framework for designing congestion-aware deterministic routing.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

Inter-process Communication Using Pipes in FPGA-Based Adaptive Computing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010



Scalability of weak consistency in NoC based multicore architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

QoS scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin.
Proceedings of the 28th International Conference on Computer Design, 2010

A Low Delay Multiple Reader Passive RFID System Using Orthogonal TH-PPM IR-UWB.
Proceedings of the 19th International Conference on Computer Communications and Networks, 2010

COSMO: CO-Simulation with MATLAB and OMNeT++ for Indoor Wireless Networks.
Proceedings of the Global Communications Conference, 2010

FPGA-based adaptive computing for correlated multi-stream processing.
Proceedings of the Design, Automation and Test in Europe, 2010

Optimal regulation of traffic flows in networks-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2010

Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Scalability of relaxed consistency models in NoC based multicore architectures.
SIGARCH Computer Architecture News, 2009

Analyzing Credit-Based Router-to-Router Flow Control for On-Chip Networks.
IEICE Transactions, 2009

Worst-Case Flit and Packet Delay Bounds in Wormhole Networks on Chip.
IEICE Transactions, 2009

Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks.
Proceedings of the 69th IEEE Vehicular Technology Conference, 2009

A flow regulator for On-Chip Communication.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

A Reconfigurable Design Framework for FPGA Adaptive Computing.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Scalability of network-on-chip communication architecture for 3-D meshes.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

From 2D to 3D NoCs: A case study on worst-case communication performance.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Run-time Partial Reconfiguration speed investigation and architectural design space exploration.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Exploration of Slot Allocation for On-Chip TDM Virtual Circuits.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Flow regulation for on-chip communication.
Proceedings of the Design, Automation and Test in Europe, 2009

Applying network calculus for performance analysis of self-similar traffic in on-chip networks.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Analysis of communication delay bounds for network on chips.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

3-D memory organization and performance analysis for multi-processor network-on-chip architecture.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
TDM Virtual-Circuit Configuration for Network-on-Chip.
IEEE Trans. VLSI Syst., 2008

ATCA-based computation platform for data acquisition and triggering in particle physics experiments.
Proceedings of the FPL 2008, 2008

System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Dynamic TDM virtual circuit implementation for NoC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Design and Analysis of On-Chip Communication for Network-on-Chip Platforms.
PhD thesis, 2007

Admitting and ejecting flits in wormhole-switched networks on chip.
IET Computers & Digital Techniques, 2007

Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Hardware/Software Co-design of a General-Purpose Computation Platform in Particle Physics.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Traffic Splitting with Network Calculus for Mesh Sensor Networks.
Proceedings of the Future Generation Communication and Networking, 2007

Layered Switching for Networks on Chip.
Proceedings of the 44th Design Automation Conference, 2007

2006
Connection-oriented Multicasting in Wormhole-switched Networks on Chip.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Evaluation of on-chip networks using deflection routing.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005
Traffic Configuration for Evaluating Networks on Chips.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Refinement of Perfectly Synchronous Communication Model.
Proceedings of the Forum on specification and Design Languages, 2005

Feasibility analysis of messages for on-chip networks using wormhole routing.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2003
Development and Application of Design Transformations in ForSyDe.
Proceedings of the 2003 Design, 2003

NoC Application Programming Interfaces.
Proceedings of the Networks on Chip, 2003

2002
A Case Study of Hardware and Software Synthesis in ForSyDe.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002


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