Axel Jantsch

According to our database1, Axel Jantsch authored at least 259 papers between 1994 and 2019.

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Bibliography

2019
Self-Adaptive QoS Management of Computation and Communication Resources in Many-Core SoCs.
ACM Trans. Embedded Comput. Syst., 2019

Efficient Design-for-Test Approach for Networks-on-Chip.
IEEE Trans. Computers, 2019

Model-free condition monitoring with confidence.
Int. J. Computer Integrated Manufacturing, 2019

On-Chip Dynamic Resource Management.
Foundations and Trends in Electronic Design Automation, 2019

Computer-aided Arrhythmia Diagnosis with Bio-signal Processing: A Survey of Trends and Techniques.
ACM Comput. Surv., 2019

Resource Constrained Self-Aware Cyber-Physical Systems (Tutorial).
Proceedings of the IEEE 4th International Workshops on Foundations and Applications of Self* Systems, 2019

Distributed SDN architecture for NoC-based many-core SoCs.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

MemGANs: Memory Management for Energy-Efficient Acceleration of Complex Computations in Hardware Architectures for Generative Adversarial Networks.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Dynamic Computation Migration at the Edge: Is There an Optimal Choice?
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Goal-Driven Autonomy for Efficient On-chip Resource Management: Transforming Objectives to Goals.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Towards a Formal Model of Recursive Self-Reflection.
Proceedings of the Workshop on Autonomous Systems Design, 2019

TrojanZero: Switching Activity-Aware Design of Undetectable Hardware Trojans with Zero Power and Area Footprint.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Dynamic Constraints for Mixed-Criticality Systems.
Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019

Energy-efficient and Reliable Wearable Internet-of-Things through Fog-Assisted Dynamic Goal Management.
Proceedings of the 10th International Conference on Ambient Systems, Networks and Technologies (ANT 2019) / The 2nd International Conference on Emerging Data and Industry 4.0 (EDI40 2019) / Affiliated Workshops, April 29, 2019

2018
Design Methodology for Responsive and Rrobust MIMO Control of Heterogeneous Multicores.
IEEE Trans. Multi-Scale Computing Systems, 2018

Weighted Quantization-Regularization in DNNs for Weight Memory Minimization Toward HW Implementation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

adBoost: Thermal Aware Performance Boosting Through Dark Silicon Patterning.
IEEE Trans. Computers, 2018

SmartDPM: Machine Learning-Based Dynamic Power Management for Multi-Core Microprocessors.
J. Low Power Electronics, 2018

HDGM: Hierarchical Dynamic Goal Management for Many-Core Resource Allocation.
Embedded Systems Letters, 2018

SAMBA - an architecture for adaptive cognitive control of distributed Cyber-Physical Production Systems based on its self-awareness.
Elektrotechnik und Informationstechnik, 2018

TrojanZero: Switching Activity-Aware Design of Undetectable Hardware Trojans with Zero Power and Area Footprint.
CoRR, 2018

Goal Formulation: Abstracting Dynamic Objectives for Efficient On-chip Resource Allocation.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

VELS: VHDL E-Learning System for Automatic Generation and Evaluation of Per-Student Randomized Assignments.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Hierarchical dynamic goal management for IoT systems.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Enhancement of Classification of Small Data Sets Using Self-awareness - An Iris Flower Case-Study.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Applicability of Context-Aware Health Monitoring to Hydraulic Circuits.
Proceedings of the IECON 2018, 2018

ADDHard: Arrhythmia Detection with Digital Hardware by Learning ECG Signal.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Trends in On-chip Dynamic Resource Management.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Resource Management for Mixed-Criticality Systems on Multi-core Platforms with Focus on Communication.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

SPECTR: Formal Supervisory Control and Coordination for Many-core Systems Resource Management.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
ForSyDe: System Design Using a Functional Language and Models of Computation.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon Era.
IEEE Trans. VLSI Syst., 2017

Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient Applications.
IEEE Trans. VLSI Syst., 2017

Minimizing the system impact of router faults by means of reconfiguration and adaptive routing.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

Self-Awareness in Systems on Chip - A Survey.
IEEE Design & Test, 2017

Guest Editorial: Special Issue on Self-Aware Systems on Chip.
IEEE Design & Test, 2017

Can Dark Silicon Be Exploited to Prolong System Lifetime?
IEEE Design & Test, 2017

Towards Verification of Uncertain Cyber-Physical Systems.
Proceedings of the Proceedings 3rd International Workshop on Symbolic and Numerical Methods for Reachability Analysis, 2017

Parallelized Flight Path Prediction using a Graphics Processing Unit.
Proceedings of the 12th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications (VISIGRAPP 2017) - Volume 6: VISAPP, Porto, Portugal, February 27, 2017

Empowering autonomy through self-awareness in MPSoCs.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Neural network based ECG anomaly detection on FPGA and trade-off analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

SAMBA: A self-aware health monitoring architecture for distributed industrial systems.
Proceedings of the IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, Beijing, China, October 29, 2017

Self-awareness in remote health monitoring systems using wearable electronics.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Toggle MUX: How X-Optimism Can Lead to Malicious Hardware.
Proceedings of the 54th Annual Design Automation Conference, 2017

On the design of context-aware health monitoring without a priori knowledge; an AC-Motor case-study.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2016
Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip.
IEEE Trans. VLSI Syst., 2016

Toward Smart Embedded Systems: A Self-aware System-on-Chip (SoC) Perspective.
ACM Trans. Embedded Comput. Syst., 2016

Non-Blocking Testing for Network-on-Chip.
IEEE Trans. Computers, 2016

Enhancing the Early Warning Score System Using Data Confidence.
Proceedings of the Wireless Mobile Communication and Healthcare, 2016

The Role of Self-Awareness and Hierarchical Agents in Resource Management for Many-Core Systems.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping.
Proceedings of the Fourth ACM International Workshop on Many-core Embedded Systems, 2016

Fully digital write-in scheme for multi-bit memristive storage.
Proceedings of the 13th International Conference on Electrical Engineering, 2016

Malicious LUT: a stealthy FPGA trojan injected and triggered by the design flow.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Approximation knob: power capping meets energy efficiency.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Comprehensive Observation and its Role in Self-Awareness; An Emotion Recognition System Example.
Proceedings of the Position Papers of the 2016 Federated Conference on Computer Science and Information Systems, 2016

Optimizing the location of ECC protection in network-on-chip.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

2015
Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels.
ACM Trans. Design Autom. Electr. Syst., 2015

Zero-load predictive model for performance analysis in deflection routing NoCs.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips.
JSW, 2015

MultiCS: Circuit switched NoC with multiple sub-networks and sub-channels.
Journal of Systems Architecture - Embedded Systems Design, 2015

Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications.
J. Electrical and Computer Engineering, 2015

Building reliable systems-on-chip in nanoscale technologies.
Elektrotechnik und Informationstechnik, 2015

The Benefits of Self-Awareness and Attention in Fog and Mist Computing.
IEEE Computer, 2015

A Routing-Level Solution for Fault Detection, Masking, and Tolerance in NoCs.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Highway in TDM NoCs.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

MapPro: Proactive Runtime Mapping for Dynamic Workloads by Quantifying Ripple Effect of Applications on Networks-on-Chip.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Design of Fault-Tolerant and Reliable Networks-on-Chip.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Dark silicon aware runtime mapping for many-core systems: A patterning approach.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Self-Aware Cyber-Physical Systems-on-Chip.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Memristors' Potential for Multi-bit Storage and Pattern Learning.
Proceedings of the 2015 IEEE European Modelling Symposium, 2015

A packet-switched interconnect for many-core systems with BE and RT service.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Exploring stacked main memory architecture for 3D GPGPUs.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Performance analysis of on-chip bufferless router with multi-ejection ports.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
A Fair and Maximal Allocator for Single-Cycle On-Chip Homogeneous Resource Allocation.
IEEE Trans. VLSI Syst., 2014

A survey of memory architecture for 3D chip multi-processors.
Microprocessors and Microsystems - Embedded Hardware Design, 2014

Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs.
IEICE Electronic Express, 2014

Editorial introduction - Special issue on languages, models and model based design for embedded systems.
Design Autom. for Emb. Sys., 2014

Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Dark silicon aware power management for manycore systems under dynamic workloads.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Rescuing healthy cores against disabled routers.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Parallel probe based dynamic connection setup in TDM NoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A framework of awareness for artificial subjects.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

2013
An Analytical Latency Model for Networks-on-Chip.
IEEE Trans. VLSI Syst., 2013

Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router.
IEEE Trans. VLSI Syst., 2013

Scalability Analysis of Memory Consistency Models in NoC-Based Distributed Shared Memory SoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Methods for fault tolerance in networks-on-chip.
ACM Comput. Surv., 2013

Mathematical formalisms for performance evaluation of networks-on-chip.
ACM Comput. Surv., 2013

Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property.
Computers & Electrical Engineering, 2013

Costs and benefits of flexibility in spatial division circuit switched networks-on-chip.
Proceedings of the Network on Chip Architectures, 2013

Efficient distributed memory management in a multi-core H.264 decoder on FPGA.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Performance Analysis of Reconfigurations in Adaptive Real-Time Streaming Applications.
ACM Trans. Embedded Comput. Syst., 2012

TPSS: A Flexible Hardware Support for Unicast and Multicast on Network-on-Chip.
JCP, 2012

A Survey of FPGA Dynamic Reconfiguration Design Methodology and Applications.
IJERTCS, 2012

Performance Analysis of Flow-Based Traffic Splitting Strategy on Cluster-Mesh Sensor Networks.
IJDSN, 2012

Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip.
IEICE Transactions, 2012

A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip.
IEICE Transactions, 2012

Self-selection pseudo- circuit: a clever crossbar pre-allocation.
IEICE Electronic Express, 2012

Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation.
Proceedings of the PECCS 2012, 2012

System-level evaluation of sensor networks deployment strategies: Coverage, lifetime and cost.
Proceedings of the 8th International Wireless Communications and Mobile Computing Conference, 2012

Scalability analysis of release and sequential consistency models in NoC based multicore systems.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Architecture Support and Comparison of Three Memory Consistency Models in NoC Based Systems.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Analytical approaches for performance evaluation of networks-on-chip.
Proceedings of the 15th International Conference on Compilers, 2012

2011
The Promises and Limitations of 3-D Integration.
Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

Hybrid Distributed Shared Memory Space in Multi-core Processors.
JSW, 2011

Cooperative communication based barrier synchronization in on-chip mesh architectures.
IEICE Electronic Express, 2011

Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations.
Embedded Systems Letters, 2011

FPGA-Based Particle Recognition in the HADES Experiment.
IEEE Design & Test of Computers, 2011

A High-End Reconfigurable Computation Platform for Nuclear and Particle Physics Experiments.
Computing in Science and Engineering, 2011

Modeling and analysis of Rayleigh fading channels using stochastic network calculus.
Proceedings of the 2011 IEEE Wireless Communications and Networking Conference, 2011

3-D integration and the limits of silicon computation.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Network-on-Chip multicasting with low latency path setup.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Concept and design of exhaustive-parallel search algorithm for Network-on-Chip.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Stochastic coverage in event-driven sensor networks.
Proceedings of the IEEE 22nd International Symposium on Personal, 2011

Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks.
Proceedings of the NOCS 2011, 2011

A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Power-efficient tree-based multicast support for Networks-on-Chip.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Evaluation of deflection routing on various NoC topologies.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

FPGA-Based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
Guest Editorial: Special Section on the ACM/IEEE Symposium on Networks-on-Chip 2009.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Buffer Optimization in Network-on-Chip Through Flow Regulation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Run-Time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips.
Proceedings of the Third International Symposium on Parallel Architectures, 2010

A Worst Case Performance Model for TDM Virtual Circuit in NoCs.
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2010

A framework for designing congestion-aware deterministic routing.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

Inter-process Communication Using Pipes in FPGA-Based Adaptive Computing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010



Scalability of weak consistency in NoC based multicore architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

HetMoC: Heterogeneous Modelling in SystemC.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routing.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2010

FPGA-based adaptive computing for correlated multi-stream processing.
Proceedings of the Design, Automation and Test in Europe, 2010

Optimal regulation of traffic flows in networks-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2010

Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller.
Proceedings of the Design, Automation and Test in Europe, 2010

Constrained global scheduling of streaming applications on MPSoCs.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Scalability of relaxed consistency models in NoC based multicore architectures.
SIGARCH Computer Architecture News, 2009

Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks.
Proceedings of the 69th IEEE Vehicular Technology Conference, 2009

A flow regulator for On-Chip Communication.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

A Reconfigurable Design Framework for FPGA Adaptive Computing.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Scalability of network-on-chip communication architecture for 3-D meshes.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

High-level estimation and trade-off analysis for adaptive real-time systems.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Run-time Partial Reconfiguration speed investigation and architectural design space exploration.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures.
Proceedings of the Design, Automation and Test in Europe, 2009

Priority based forced requeue to reduce worst-case latencies for bursty traffic.
Proceedings of the Design, Automation and Test in Europe, 2009

Flow regulation for on-chip communication.
Proceedings of the Design, Automation and Test in Europe, 2009

Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Models of Embedded Computation for Distributed Embedded Systems.
Proceedings of the Embedded Systems Design and Verification, 2009

2008
TDM Virtual-Circuit Configuration for Network-on-Chip.
IEEE Trans. VLSI Syst., 2008

A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration.
ACM Trans. Design Autom. Electr. Syst., 2008

Application and Verification of Local Nonsemantic-Preserving Transformations in System Design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Low-power and error protection coding for network-on-chip traffic.
IET Computers & Digital Techniques, 2008

Modeling Communication with Synchronized Environments.
Fundam. Inform., 2008

Modelling Adaptive Systems in ForSyDe.
Electr. Notes Theor. Comput. Sci., 2008

C-Based Design of Heterogeneous Embedded Systems.
EURASIP J. Emb. Sys., 2008

SML-Sys: a functional framework with multiple models of computation for modeling heterogeneous system.
Design Autom. for Emb. Sys., 2008

ATCA-based computation platform for data acquisition and triggering in particle physics experiments.
Proceedings of the FPL 2008, 2008

Performance analysis of reconfiguration in adaptive real-time streaming applications.
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008

Energy efficient streaming applications with guaranteed throughput on MPSoCs.
Proceedings of the 8th ACM & IEEE International conference on Embedded software, 2008

System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Heterogeneous System-level Specification Using SystemC.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
EWD: A metamodeling driven customizable multi-MoC system modeling framework.
ACM Trans. Design Autom. Electr. Syst., 2007

Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology.
Trans. HiPEAC, 2007

Admitting and ejecting flits in wormhole-switched networks on chip.
IET Computers & Digital Techniques, 2007

DATE 07 workshop on diagnostic services in NoCs.
IEEE Design & Test of Computers, 2007

Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

A Study of NoC Exit Strategies.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Towards Open Network-on-Chip Benchmarks.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

An Analytical Approach for Dimensioning Mixed Traffic Networks.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Hardware/Software Co-design of a General-Purpose Computation Platform in Particle Physics.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems.
Proceedings of the FPL 2007, 2007

Traffic Splitting with Network Calculus for Mesh Sensor Networks.
Proceedings of the Future Generation Communication and Networking, 2007

Network Calculus Applied to Verification of Memory Access Performance in SoCs.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

Increasing NoC Performance and Utilisation using a Dual Packet Exit Strategy.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Layered Switching for Networks on Chip.
Proceedings of the 44th Design Automation Conference, 2007

Synchronization after design refinements with sensitive delay elements.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006
On-Chip Distributed Architectures.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

An algorithm for electing cluster heads based on maximum residual energy.
Proceedings of the International Conference on Wireless Communications and Mobile Computing, 2006

Connection-oriented Multicasting in Wormhole-switched Networks on Chip.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Evaluation of on-chip networks using deflection routing.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

A High Level Power Model for the Nostrum NoC.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Adaptive Power Management for the On-Chip Communication Network.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration.
Proceedings of the 43rd Design Automation Conference, 2006

MPSoC ECG biochip: a multiprocessor system-on-chip for real-time human heart monitoring and analysis.
Proceedings of the Third Conference on Computing Frontiers, 2006

Communicating with Synchronized Environments.
Proceedings of the Sixth International Conference on Application of Concurrency to System Design (ACSD 2006), 2006

Models of Computation for Networks on Chip.
Proceedings of the Sixth International Conference on Application of Concurrency to System Design (ACSD 2006), 2006

2005
Models of Embedded Computation.
Proceedings of the Embedded Systems Handbook., 2005

Traffic Configuration for Evaluating Networks on Chips.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Power analysis of link level and end-to-end data protection in networks on chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

System level verification of digital signal processing applications based on the polynomial abstraction technique.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Modelling Environment for Heterogeneous Systems based on MoCs.
Proceedings of the Forum on specification and Design Languages, 2005

Refinement of Perfectly Synchronous Communication Model.
Proceedings of the Forum on specification and Design Languages, 2005

Feasibility analysis of messages for on-chip networks using wormhole routing.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
System modeling and transformational design refinement in ForSyDe [formal system design].
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Special issue on networks on chip.
Journal of Systems Architecture, 2004

A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime.
Integration, 2004

The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits.
Proceedings of the 2004 Design, 2004

Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip.
Proceedings of the 2004 Design, 2004

System Design for DSP Applications Using the MASIC Methodology.
Proceedings of the 2004 Design, 2004

System design for DSP applications in transaction level modeling paradigm.
Proceedings of the 41th Design Automation Conference, 2004

2003
Extending Platform-Based Design to Network on Chip Systems.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Simulation and Analysis of Embedded DSP Systems Using Petri Nets.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

NoCs: A new Contract between Hardware and Software.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

Development and Application of Design Transformations in ForSyDe.
Proceedings of the 2003 Design, 2003

Load Distribution with the Proximity Congestion Awareness in a Network on Chip.
Proceedings of the 2003 Design, 2003

Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology.
Proceedings of the 2003 Design, 2003

A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Verification of design decisions in ForSyDe.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Will Networks on Chip Close the Productivity Gap?
Proceedings of the Networks on Chip, 2003

Modeling embedded systems and SoCs - concurrency and time in models of computation.
The Morgan Kaufmann series in systems on silicon, Elsevier Morgan Kaufmann, ISBN: 978-1-55860-925-9, 2003

2002
A Network on Chip Architecture and Design Methodology.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

A Case Study of Hardware and Software Synthesis in ForSyDe.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Transformation based communication and clock domain refinement for system design.
Proceedings of the 39th Design Automation Conference, 2002

FPGA resource and timing estimation from Matlab execution traces.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
Modeling of mixed control and dataflow systems in MASCOT.
IEEE Trans. VLSI Syst., 2001

Grammar-based design of embedded systems.
Journal of Systems Architecture, 2001

Device Driver and DMA Controller Synthesis from HW /SW Communication Protocol Specifications.
Design Autom. for Emb. Sys., 2001

Control and communication performance analysis of embedded DSP systems in the MASIC methodology.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Performance analysis with confidence intervals for embedded software processes.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

The usage of stochastic processes in embedded system specifications.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000
A Metamodel for Studying Concepts in Electronic System Design.
IEEE Design & Test of Computers, 2000

Functional Validation of Mixed Hardware/Software Systems based on Specification, Partitioning, and Simulation of Test Cases.
Design Autom. for Emb. Sys., 2000

A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization.
Proceedings of the Field-Programmable Logic and Applications, 2000

Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors.
Proceedings of the 2000 Design, 2000

MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow.
Proceedings of the 2000 Design, 2000

On the roles of functions and objects in system specification.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999
Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Synthesis of DMA Controllers from Architecture Independent Descriptions of HW/SW Communication Protocols.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Operating System Sensitive Device Driver Synthesis from Implementation Independent Protocol Specification.
Proceedings of the 1999 Design, 1999

The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems.
Proceedings of the 1999 Design, 1999

System synthesis utilizing a layered functional model.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
An Object-Oriented Concept for Intelligent Library Functions.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Grammar Based Modelling and Synthesis of Device Drivers and Bus Interfaces.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997
System oriented VLSI curriculum at KTH.
Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997

1996
A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A Rule-Based Approach for Improving Allocation of Filter Structures in HLS.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1994
DSP Development with Full-Speed Prototyping Based on HW/SW Codesign Techniques.
Proceedings of the Field-Programmable Logic, 1994

Hardware/software partitioning and minimizing memory interface traffic.
Proceedings of the Proceedings EURO-DAC'94, 1994


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