Axel Jantsch

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

adBoost: Thermal Aware Performance Boosting Through Dark Silicon Patterning.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

SmartDPM: Machine Learning-Based Dynamic Power Management for Multi-Core Microprocessors.

[BibT_eX]

[DOI]

Sai Manoj P. D.

Muhammad Shafique

J. Low Power Electron., 2018

HDGM: Hierarchical Dynamic Goal Management for Many-Core Resource Allocation.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2018

SAMBA - an architecture for adaptive cognitive control of distributed Cyber-Physical Production Systems based on its self-awareness.

[BibT_eX]

[DOI]

Elektrotech. Informationstechnik, 2018

Guest Editorial: Special Issue on Self-Aware Systems on Chip.

[BibT_eX]

[DOI]

IEEE Des. Test, 2018

Goal Formulation: Abstracting Dynamic Objectives for Efficient On-chip Resource Allocation.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

VELS: VHDL E-Learning System for Automatic Generation and Evaluation of Per-Student Randomized Assignments.

[BibT_eX]

[DOI]

Martin Mosbeck

Daniel Hauer

Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Hierarchical dynamic goal management for IoT systems.

[BibT_eX]

[DOI]

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Enhancement of Classification of Small Data Sets Using Self-awareness - An Iris Flower Case-Study.

[BibT_eX]

[DOI]

Hedyeh A. Kholerdi

Nima Taherinejad

Sai Manoj Pudukotai Dinakarrao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Applicability of Context-Aware Health Monitoring to Hydraulic Circuits.

[BibT_eX]

[DOI]

Proceedings of the IECON 2018, 2018

ADDHard: Arrhythmia Detection with Digital Hardware by Learning ECG Signal.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Trends in On-chip Dynamic Resource Management.

[BibT_eX]

[DOI]

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Resource Management for Mixed-Criticality Systems on Multi-core Platforms with Focus on Communication.

[BibT_eX]

[DOI]

Robin Arbaud

David Juhasz

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

SPECTR: Formal Supervisory Control and Coordination for Many-core Systems Resource Management.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017

ForSyDe: System Design Using a Functional Language and Models of Computation.

[BibT_eX]

[DOI]

Seyed-Hosein Attarzadeh-Niaki

Proceedings of the Handbook of Hardware/Software Codesign., 2017

Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon Era.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Minimizing the system impact of router faults by means of reconfiguration and adaptive routing.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

Self-Awareness in Systems on Chip - A Survey.

[BibT_eX]

[DOI]

IEEE Des. Test, 2017

Can Dark Silicon Be Exploited to Prolong System Lifetime?

[BibT_eX]

[DOI]

IEEE Des. Test, 2017

Towards Verification of Uncertain Cyber-Physical Systems.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 3rd International Workshop on Symbolic and Numerical Methods for Reachability Analysis, 2017

Parallelized Flight Path Prediction using a Graphics Processing Unit.

[BibT_eX]

[DOI]

Maximilian Götzinger

Martin Pongratz

Proceedings of the 12th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications (VISIGRAPP 2017) - Volume 6: VISAPP, Porto, Portugal, February 27, 2017

Empowering autonomy through self-awareness in MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Neural network based ECG anomaly detection on FPGA and trade-off analysis.

[BibT_eX]

[DOI]

Matthias Wess

Sai Manoj P. D.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

SAMBA: A self-aware health monitoring architecture for distributed industrial systems.

[BibT_eX]

[DOI]

Proceedings of the IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, Beijing, China, October 29, 2017

Self-awareness in remote health monitoring systems using wearable electronics.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Toggle MUX: How X-Optimism Can Lead to Malicious Hardware.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

On the design of context-aware health monitoring without a priori knowledge; an AC-Motor case-study.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2016

Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Toward Smart Embedded Systems: A Self-aware System-on-Chip (SoC) Perspective.

[BibT_eX]

[DOI]

Santanu Sarma

ACM Trans. Embed. Comput. Syst., 2016

Non-Blocking Testing for Network-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Enhancing the Early Warning Score System Using Data Confidence.

[BibT_eX]

[DOI]

Proceedings of the Wireless Mobile Communication and Healthcare, 2016

The Role of Self-Awareness and Hierarchical Agents in Resource Management for Many-Core Systems.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping.

[BibT_eX]

[DOI]

Proceedings of the Fourth ACM International Workshop on Many-core Embedded Systems, 2016

Fully digital write-in scheme for multi-bit memristive storage.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Electrical Engineering, 2016

Malicious LUT: a stealthy FPGA trojan injected and triggered by the design flow.

[BibT_eX]

[DOI]

Christian Krieg

Clifford Wolf

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Approximation knob: power capping meets energy efficiency.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Comprehensive Observation and its Role in Self-Awareness; An Emotion Recognition System Example.

[BibT_eX]

[DOI]

Nima Taherinejad

David Pollreisz

Proceedings of the Position Papers of the 2016 Federated Conference on Computer Science and Information Systems, 2016

Optimizing the location of ECC protection in network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

2015

Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

Zero-load predictive model for performance analysis in deflection routing NoCs.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips.

[BibT_eX]

[DOI]

J. Softw., 2015

MultiCS: Circuit switched NoC with multiple sub-networks and sub-channels.

[BibT_eX]

[DOI]

Varadan Savulimedu Veeravalli

J. Syst. Archit., 2015

Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2015

Building reliable systems-on-chip in nanoscale technologies.

[BibT_eX]

[DOI]

Elektrotech. Informationstechnik, 2015

The Benefits of Self-Awareness and Attention in Fog and Mist Computing.

[BibT_eX]

[DOI]

Computer, 2015

A Routing-Level Solution for Fault Detection, Masking, and Tolerance in NoCs.

[BibT_eX]

[DOI]

Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Highway in TDM NoCs.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

MapPro: Proactive Runtime Mapping for Dynamic Workloads by Quantifying Ripple Effect of Applications on Networks-on-Chip.

[BibT_eX]

[DOI]

Pasi Liljeberg

Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Design of Fault-Tolerant and Reliable Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Dark silicon aware runtime mapping for many-core systems: A patterning approach.

[BibT_eX]

[DOI]

Pasi Liljeberg

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Self-Aware Cyber-Physical Systems-on-Chip.

[BibT_eX]

[DOI]

Santanu Sarma

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Memristors' Potential for Multi-bit Storage and Pattern Learning.

[BibT_eX]

[DOI]

Nima Taherinejad

Sai Manoj P. D.

Proceedings of the 2015 IEEE European Modelling Symposium, 2015

A packet-switched interconnect for many-core systems with BE and RT service.

[BibT_eX]

[DOI]

Runan Ma

Zhida Hui

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Exploring stacked main memory architecture for 3D GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Performance analysis of on-chip bufferless router with multi-ejection ports.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

A Fair and Maximal Allocator for Single-Cycle On-Chip Homogeneous Resource Allocation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

A survey of memory architecture for 3D chip multi-processors.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

Editorial introduction - Special issue on languages, models and model based design for embedded systems.

[BibT_eX]

[DOI]

Martin Radetzki

Des. Autom. Embed. Syst., 2014

Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Dark silicon aware power management for manycore systems under dynamic workloads.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Rescuing healthy cores against disabled routers.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Parallel probe based dynamic connection setup in TDM NoCs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A framework of awareness for artificial subjects.

[BibT_eX]

[DOI]

Kalle Tammemäe

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

2013

An Analytical Latency Model for Networks-on-Chip.

[BibT_eX]

[DOI]

Abbas Eslami Kiasari

IEEE Trans. Very Large Scale Integr. Syst., 2013

Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Scalability Analysis of Memory Consistency Models in NoC-Based Distributed Shared Memory SoCs.

[BibT_eX]

[DOI]

Abdul Naeem

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Methods for fault tolerance in networks-on-chip.

[BibT_eX]

[DOI]

ACM Comput. Surv., 2013

Mathematical formalisms for performance evaluation of networks-on-chip.

[BibT_eX]

[DOI]

Abbas Eslami Kiasari

ACM Comput. Surv., 2013

Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2013

Costs and benefits of flexibility in spatial division circuit switched networks-on-chip.

[BibT_eX]

[DOI]

Ahsen Ejaz

Proceedings of the Network on Chip Architectures, 2013

Efficient distributed memory management in a multi-core H.264 decoder on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on System on Chip, 2013

Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

Performance Analysis of Reconfigurations in Adaptive Real-Time Streaming Applications.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2012

TPSS: A Flexible Hardware Support for Unicast and Multicast on Network-on-Chip.

[BibT_eX]

[DOI]

J. Comput., 2012

A Survey of FPGA Dynamic Reconfiguration Design Methodology and Applications.

[BibT_eX]

[DOI]

Int. J. Embed. Real Time Commun. Syst., 2012

Performance Analysis of Flow-Based Traffic Splitting Strategy on Cluster-Mesh Sensor Networks.

[BibT_eX]

[DOI]

Int. J. Distributed Sens. Networks, 2012

Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2012

A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2012

Self-selection pseudo- circuit: a clever crossbar pre-allocation.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2012

Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation.

[BibT_eX]

Proceedings of the PECCS 2012, 2012

System-level evaluation of sensor networks deployment strategies: Coverage, lifetime and cost.

[BibT_eX]

[DOI]

Huimin She

Proceedings of the 8th International Wireless Communications and Mobile Computing Conference, 2012

Scalability analysis of release and sequential consistency models in NoC based multicore systems.

[BibT_eX]

[DOI]

Abdul Naeem

Proceedings of the 2012 International Symposium on System on Chip, 2012

Architecture Support and Comparison of Three Memory Consistency Models in NoC Based Systems.

[BibT_eX]

[DOI]

Abdul Naeem

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Analytical approaches for performance evaluation of networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Compilers, 2012

2011

The Promises and Limitations of 3-D Integration.

[BibT_eX]

[DOI]

Shaghayeghsadat Tabatabaei

Matthew Grange

Dinesh Pamunuwa

Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

Hybrid Distributed Shared Memory Space in Multi-core Processors.

[BibT_eX]

[DOI]

J. Softw., 2011

Cooperative communication based barrier synchronization in on-chip mesh architectures.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2011

Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations.

[BibT_eX]

[DOI]

Iraklis Anagnostopoulos

IEEE Embed. Syst. Lett., 2011

FPGA-Based Particle Recognition in the HADES Experiment.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2011

A High-End Reconfigurable Computation Platform for Nuclear and Particle Physics Experiments.

[BibT_eX]

[DOI]

Comput. Sci. Eng., 2011

Modeling and analysis of Rayleigh fading channels using stochastic network calculus.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE Wireless Communications and Networking Conference, 2011

3-D integration and the limits of silicon computation.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Network-on-Chip multicasting with low latency path setup.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Concept and design of exhaustive-parallel search algorithm for Network-on-Chip.

[BibT_eX]

[DOI]

Meganathan Deivasigamani

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Stochastic coverage in event-driven sensor networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE 22nd International Symposium on Personal, 2011

Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2011, 2011

A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems.

[BibT_eX]

[DOI]

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Power-efficient tree-based multicast support for Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Evaluation of deflection routing on various NoC topologies.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

FPGA-Based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010

Guest Editorial: Special Section on the ACM/IEEE Symposium on Networks-on-Chip 2009.

[BibT_eX]

[DOI]

Radu Marculescu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Buffer Optimization in Network-on-Chip Through Flow Regulation.

[BibT_eX]

[DOI]

Mohammad Hossien Yaghmaee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Reducing FPGA Reconfiguration Time Overhead using Virtual Configurations.

[BibT_eX]

Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010

Run-Time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips.

[BibT_eX]

[DOI]

Proceedings of the Third International Symposium on Parallel Architectures, 2010

A Worst Case Performance Model for TDM Virtual Circuit in NoCs.

[BibT_eX]

[DOI]

Zhipeng Chen

Proceedings of the Network and Parallel Computing, IFIP International Conference, 2010

A framework for designing congestion-aware deterministic routing.

[BibT_eX]

[DOI]

Abbas Eslami Kiasari

Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

Inter-process Communication Using Pipes in FPGA-Based Adaptive Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

The MOSART Mapping Optimization for Multi-Core ARchiTectures.

[BibT_eX]

[DOI]

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Scalability of weak consistency in NoC based multicore architectures.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

HetMoC: Heterogeneous Modelling in SystemC.

[BibT_eX]

Proceedings of the 2010 Forum on specification & Design Languages, 2010

Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routing.

[BibT_eX]

[DOI]

Amr Helmy

Laurence Pierre

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

FPGA-based adaptive computing for correlated multi-stream processing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Optimal regulation of traffic flows in networks-on-chip.

[BibT_eX]

[DOI]

Mohammad Hossien Yaghmaee

Proceedings of the Design, Automation and Test in Europe, 2010

Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Constrained global scheduling of streaming applications on MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Scalability of relaxed consistency models in NoC based multicore architectures.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2009

Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the 69th IEEE Vehicular Technology Conference, 2009

A flow regulator for On-Chip Communication.

[BibT_eX]

[DOI]

Dimitris Brachos

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

A Reconfigurable Design Framework for FPGA Adaptive Computing.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Scalability of network-on-chip communication architecture for 3-D meshes.

[BibT_eX]

[DOI]

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

High-level estimation and trade-off analysis for adaptive real-time systems.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Run-time Partial Reconfiguration speed investigation and architectural design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Priority based forced requeue to reduce worst-case latencies for bursty traffic.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Flow regulation for on-chip communication.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh.

[BibT_eX]

[DOI]

Matt Grange

Proceedings of the IEEE International Conference on 3D System Integration, 2009

Models of Embedded Computation for Distributed Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Embedded Systems Design and Verification, 2009

2008

TDM Virtual-Circuit Configuration for Network-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Application and Verification of Local Nonsemantic-Preserving Transformations in System Design.

[BibT_eX]

[DOI]

Tarvo Raudvere

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Low-power and error protection coding for network-on-chip traffic.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2008

Modeling Communication with Synchronized Environments.

[BibT_eX]

[DOI]

Tiberiu Seceleanu

Fundam. Informaticae, 2008

C-Based Design of Heterogeneous Embedded Systems.

[BibT_eX]

[DOI]

EURASIP J. Embed. Syst., 2008

SML-Sys: a functional framework with multiple models of computation for modeling heterogeneous system.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2008

ATCA-based computation platform for data acquisition and triggering in particle physics experiments.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

Performance analysis of reconfiguration in adaptive real-time streaming applications.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008

Energy efficient streaming applications with guaranteed throughput on MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 8th ACM & IEEE International conference on Embedded software, 2008

System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip.

[BibT_eX]

[DOI]

Lei Xia

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Heterogeneous System-level Specification Using SystemC.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

2007

EWD: A metamodeling driven customizable multi-MoC system modeling framework.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology.

[BibT_eX]

[DOI]

Trans. High Perform. Embed. Archit. Compil., 2007

Admitting and ejecting flits in wormhole-switched networks on chip.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

Modelling Adaptive Systems in ForSyDe.

[BibT_eX]

[DOI]

Proceedings of the First Workshop on Verification of Adaptive Systems, 2007

DATE 07 workshop on diagnostic services in NoCs.

[BibT_eX]

[DOI]

Erik Jan Marinissen

Nicola Nicolici

IEEE Des. Test Comput., 2007

Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

A Study of NoC Exit Strategies.

[BibT_eX]

[DOI]

Proceedings of the First International Symposium on Networks-on-Chips, 2007

Towards Open Network-on-Chip Benchmarks.

[BibT_eX]

[DOI]

Proceedings of the First International Symposium on Networks-on-Chips, 2007

An Analytical Approach for Dimensioning Mixed Traffic Networks.

[BibT_eX]

[DOI]

Per Badlund

Proceedings of the First International Symposium on Networks-on-Chips, 2007

Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops.

[BibT_eX]

[DOI]

Tarvo Raudvere

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Hardware/Software Co-design of a General-Purpose Computation Platform in Particle Physics.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems.

[BibT_eX]

[DOI]

Anne-Marie Fouilliart

Marcos Martínez

Proceedings of the FPL 2007, 2007

Traffic Splitting with Network Calculus for Mesh Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the Future Generation Communication and Networking, 2007

Network Calculus Applied to Verification of Memory Access Performance in SoCs.

[BibT_eX]

[DOI]

Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

Increasing NoC Performance and Utilisation using a Dual Packet Exit Strategy.

[BibT_eX]

[DOI]

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Layered Switching for Networks on Chip.

[BibT_eX]

[DOI]

Ming Liu

Proceedings of the 44th Design Automation Conference, 2007

Synchronization after design refinements with sensitive delay elements.

[BibT_eX]

[DOI]

Tarvo Raudvere

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions.

[BibT_eX]

[DOI]

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006

On-Chip Distributed Architectures.

[BibT_eX]

[DOI]

Tiberiu Seceleanu

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

An algorithm for electing cluster heads based on maximum residual energy.

[BibT_eX]

[DOI]

Weixing Wang

Proceedings of the International Conference on Wireless Communications and Mobile Computing, 2006

Connection-oriented Multicasting in Wormhole-switched Networks on Chip.

[BibT_eX]

[DOI]

Bei Yin

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Evaluation of on-chip networks using deflection routing.

[BibT_eX]

[DOI]

Mingchen Zhong

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads.

[BibT_eX]

[DOI]

Rikard Thid

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

A High Level Power Model for the Nostrum NoC.

[BibT_eX]

[DOI]

Sandro Penolazzi

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Adaptive Power Management for the On-Chip Communication Network.

[BibT_eX]

[DOI]

Guang Liang

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

MPSoC ECG biochip: a multiprocessor system-on-chip for real-time human heart monitoring and analysis.

[BibT_eX]

[DOI]

Proceedings of the Third Conference on Computing Frontiers, 2006

Communicating with Synchronized Environments.

[BibT_eX]

[DOI]

Tiberiu Seceleanu

Proceedings of the Sixth International Conference on Application of Concurrency to System Design (ACSD 2006), 2006

Models of Computation for Networks on Chip.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on Application of Concurrency to System Design (ACSD 2006), 2006

2005

Models of Embedded Computation.

[BibT_eX]

[DOI]

Proceedings of the Embedded Systems Handbook., 2005

Traffic Configuration for Evaluating Networks on Chips.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Power analysis of link level and end-to-end data protection in networks on chip.

[BibT_eX]

[DOI]

Robert Lauter

Arseni Vitkovski

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

System level verification of digital signal processing applications based on the polynomial abstraction technique.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Modelling Environment for Heterogeneous Systems based on MoCs.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2005

Refinement of Perfectly Synchronous Communication Model.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2005

Feasibility analysis of messages for on-chip networks using wormhole routing.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

System modeling and transformational design refinement in ForSyDe [formal system design].

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Special issue on networks on chip.

[BibT_eX]

[DOI]

J. Syst. Archit., 2004

A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime.

[BibT_eX]

[DOI]

Integr., 2004

The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Flit admission in on-chip wormhole-switched networks with virtual channels.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on System-on-Chip, 2004

Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

System Design for DSP Applications Using the MASIC Methodology.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

System design for DSP applications in transaction level modeling paradigm.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

2003

Extending Platform-Based Design to Network on Chip Systems.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures.

[BibT_eX]

Proceedings of the IFIP VLSI-SoC 2003, 2003

Simulation and Analysis of Embedded DSP Systems Using Petri Nets.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

NoCs: A new Contract between Hardware and Software.

[BibT_eX]

[DOI]

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

Development and Application of Design Transformations in ForSyDe.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Load Distribution with the Proximity Congestion Awareness in a Network on Chip.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip.

[BibT_eX]

[DOI]

Heiko Zimmer

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Verification of design decisions in ForSyDe.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Will Networks on Chip Close the Productivity Gap?

[BibT_eX]

[DOI]

Proceedings of the Networks on Chip, 2003

Modeling embedded systems and SoCs - concurrency and time in models of computation.

[BibT_eX]

The Morgan Kaufmann series in systems on silicon, Elsevier Morgan Kaufmann, ISBN: 978-1-55860-925-9, 2003

2002

A Network on Chip Architecture and Design Methodology.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

A Case Study of Hardware and Software Synthesis in ForSyDe.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Transformation based communication and clock domain refinement for system design.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

FPGA resource and timing estimation from Matlab execution traces.

[BibT_eX]

[DOI]

Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001

Modeling of mixed control and dataflow systems in MASCOT.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Grammar-based design of embedded systems.

[BibT_eX]

[DOI]

J. Syst. Archit., 2001

Device Driver and DMA Controller Synthesis from HW /SW Communication Protocol Specifications.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2001

Control and communication performance analysis of embedded DSP systems in the MASIC methodology.

[BibT_eX]

[DOI]

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Performance analysis with confidence intervals for embedded software processes.

[BibT_eX]

[DOI]

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

The usage of stochastic processes in embedded system specifications.

[BibT_eX]

[DOI]

Wenbiao Wu

Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000

A Metamodel for Studying Concepts in Electronic System Design.

[BibT_eX]

[DOI]

Shashi Kumar

Ahmed Hemani

IEEE Des. Test Comput., 2000

Functional Validation of Mixed Hardware/Software Systems based on Specification, Partitioning, and Simulation of Test Cases.

[BibT_eX]

[DOI]

Johann Notbauer

Thomas W. Albrecht

Des. Autom. Embed. Syst., 2000

A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization.

[BibT_eX]

[DOI]

Johan Ditmar

Kjell Torkelsson

Proceedings of the Field-Programmable Logic and Applications, 2000

Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

On the roles of functions and objects in system specification.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999

Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Synthesis of DMA Controllers from Architecture Independent Descriptions of HW/SW Communication Protocols.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Operating System Sensitive Device Driver Synthesis from Implementation Independent Protocol Specification.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems.

[BibT_eX]

[DOI]

Shashi Kumar

Ahmed Hemani

Proceedings of the 1999 Design, 1999

System synthesis utilizing a layered functional model.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998

An Object-Oriented Concept for Intelligent Library Functions.

[BibT_eX]

[DOI]

Anshul Kumar

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Grammar Based Modelling and Synthesis of Device Drivers and Bus Interfaces.

[BibT_eX]

[DOI]

Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997

System oriented VLSI curriculum at KTH.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997

1996

A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A Rule-Based Approach for Improving Allocation of Filter Structures in HLS.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1994

DSP Development with Full-Speed Prototyping Based on HW/SW Codesign Techniques.

[BibT_eX]

[DOI]

Jouni Isoaho