Farakh Javid

Orcid: 0000-0002-2007-9380

According to our database1, Farakh Javid authored at least 7 papers between 2009 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Fast multidimensional optimization of analog circuits initiated by monodimensional global Peano explorations.
Integr., 2015

2013
A structured DC analysis methodology for accurate verification of analog circuits.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
A Design and Verification Methodology for Mixed-Signal Systems Using SystemC-AMS.
Proceedings of the Models, Methods, and Tools for Complex Chip Design, 2012

A unified platform for design and verification of mixed-signal systems based on SystemC AMS.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

2011
A Python-based layout-aware analog design methodology for nanometric technologies.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

A seamless representation for coupling transistor sizing with nanometric CMOS layout generation.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2009
Simulation-based hierarchical sizing and biasing of analog firm IPs.
Proceedings of the 2009 IEEE International Behavioral Modeling and Simulation Workshop, 2009


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