Ramy Iskander

According to our database1, Ramy Iskander authored at least 21 papers between 2003 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Fast extraction of predictive models for integrated circuits using n-performance Pareto fronts.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

2016
Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

An adaptive mesh refinement strategy of substrate modeling for smart power ICs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Mixed-signal PI controller in current-mode DC-DC buck converter for automotive applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Towards automatic diagnosis of minority carriers propagation problems in HV/HT automotive smart power ICs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Fast multidimensional optimization of analog circuits initiated by monodimensional global Peano explorations.
Integr., 2015

Substrate noise modeling with dedicated CAD framework for smart power ICs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Modeling, design and verification platform using SystemC AMS.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013
Hierarchical sizing and biasing of analog firm intellectual properties.
Integr., 2013

A structured DC analysis methodology for accurate verification of analog circuits.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
A Design and Verification Methodology for Mixed-Signal Systems Using SystemC-AMS.
Proceedings of the Models, Methods, and Tools for Complex Chip Design, 2012

A unified platform for design and verification of mixed-signal systems based on SystemC AMS.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

2011
A Python-based layout-aware analog design methodology for nanometric technologies.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

A seamless representation for coupling transistor sizing with nanometric CMOS layout generation.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Automatic stress effects computation based on a layout generation tool for analog IC.
Proceedings of the 2010 IEEE International Behavioral Modeling and Simulation Conference, 2010

Design and modeling of a successive approximation ADC for the electrostatic harvester of vibration energy.
Proceedings of the 2010 IEEE International Behavioral Modeling and Simulation Conference, 2010

2009
Simulation-based hierarchical sizing and biasing of analog firm IPs.
Proceedings of the 2009 IEEE International Behavioral Modeling and Simulation Workshop, 2009

2008
Connaissance et synthèse en vue de la conception et la réutilisation de circuits analogiques intégrés. (Knowledge-aware synthesis for analog integrated circuit design and reuse).
PhD thesis, 2008

2007
Systematic Offset Detection and Evaluation Using Hierarchical Graph-Based Sizing and Biasing.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2003
Synthesis of CMOS Analog Cells Using AMIGO.
Proceedings of the 2003 Design, 2003


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